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authorDave Frodin <dave.frodin@se-eng.com>2012-11-16 14:16:33 -0700
committerMarc Jones <marcj303@gmail.com>2012-11-20 23:59:54 +0100
commit73be43a139f15dfa526b0eeefb5539b35cc0902f (patch)
treecc2a2d497c9256610d33a80e3b42bb5a96f7518c /src/mainboard/amd
parent8ada1526df06cb50a82305e840a5181a3c65575f (diff)
downloadcoreboot-73be43a139f15dfa526b0eeefb5539b35cc0902f.tar.xz
Persimmon: Disable the unused GPP PCIe clocks
Change-Id: I4128af7912bec090bbd48acc1b20d0452e7a4a28 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1876 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/persimmon/mainboard.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index 4c52dc3233..5edacd3ab6 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -28,6 +28,7 @@
#include "BiosCallOuts.h"
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/amd/mtrr.h>
+#include "SBPLATFORM.h"
void set_pcie_reset(void);
void set_pcie_dereset(void);
@@ -63,6 +64,15 @@ static void persimmon_enable(device_t dev)
#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = acpi_get_sleep_type();
#endif
+
+ /* enable GPP CLK0 thru CLK1 */
+ /* disable GPP CLK2 thru SLT_GFX_CLK */
+ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
+ *(misc_mem_clk_cntrl + 0) = 0xFF;
+ *(misc_mem_clk_cntrl + 1) = 0x00;
+ *(misc_mem_clk_cntrl + 2) = 0x00;
+ *(misc_mem_clk_cntrl + 3) = 0x00;
+ *(misc_mem_clk_cntrl + 4) = 0x00;
}
struct chip_operations mainboard_ops = {