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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-07-25 18:46:46 -0600
committerMartin Roth <martinroth@google.com>2017-07-27 21:31:04 +0000
commit9df969aebfdeb6d162cd2aeb288fa4420a21953a (patch)
treec7e79f7dec871870b7e865570a706092a6541f0d /src/mainboard/amd
parentc95d6ffa7cd532243210723e43b977aa880a72e8 (diff)
downloadcoreboot-9df969aebfdeb6d162cd2aeb288fa4420a21953a.tar.xz
soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK
Add dedicated CAR setup and teardown functions and Kconfig options to force their inclusion into the build. The .S files are mostly duplicated code from the old cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Drop the BIST check like other devices. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. There are currently some early dependencies on InitReset. Future work should include: * Pull the necessary functionality from InitReset into bootblock * Move InitReset and InitEarly to car_stage_entry() and out of bootblock - Add a mechanism for the BSP to give the APs an address to call and skip most of bootblock and verstage (when available) (1) - Reunify BiosCallOuts.c and OemCustomize.c (1) During the InitReset call, the BSP enables the APs by setting core enable bits in F18F0x1DC and APs begin fetching/executing from the reset vector. The BSP waits for all APs to also reach InitReset, where they enter an endless loop. The BSP sends a command to them to execute a HLT instruction and the BSP eventually returns from InitReset. The goal would be to preserve this process but prevent APs from rerunning early code. Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/gardenia/BiosCallOuts.c88
-rw-r--r--src/mainboard/amd/gardenia/Makefile.inc3
-rw-r--r--src/mainboard/amd/gardenia/OemCustomize.c136
-rw-r--r--src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c69
-rw-r--r--src/mainboard/amd/gardenia/bootblock/OemCustomize.c155
-rw-r--r--src/mainboard/amd/gardenia/romstage.c69
6 files changed, 247 insertions, 273 deletions
diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c
index ac0ed6ad57..fd03f4e3fa 100644
--- a/src/mainboard/amd/gardenia/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c
@@ -13,83 +13,18 @@
* GNU General Public License for more details.
*/
-#include <device/pci_def.h>
-#include <device/device.h>
#include <AGESA.h>
-#include <amdlib.h>
#include <BiosCallOuts.h>
-#include <Ids.h>
-#include <heapManager.h>
#include <FchPlatform.h>
-#include <cbfs.h>
#include <soc/imc.h>
#include <soc/hudson.h>
#include <stdlib.h>
-#include <dimmSpd.h>
-#include <agesawrapper.h>
-static AGESA_STATUS Fch_Oem_config(UINT32 Func,
- UINTN FchData, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
- {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
- {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
- {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
- {AGESA_READ_SPD, agesa_ReadSpd },
- {AGESA_DO_RESET, agesa_Reset },
- {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
- {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
- {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
- {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
- {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
- {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
- {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-static const GPIO_CONTROL oem_gardenia_gpio[] = {
- /* BT radio disable */
- {14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
- | FCH_GPIO_OUTPUT_ENABLE},
- /* NFC PU */
- {64, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
- | FCH_GPIO_OUTPUT_ENABLE},
- /* NFC wake */
- {65, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
- | FCH_GPIO_OUTPUT_ENABLE},
- /* Webcam */
- {66, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
- | FCH_GPIO_OUTPUT_ENABLE},
- /* PCIe presence detect */
- {69, Function0, FCH_GPIO_PULL_UP_ENABLE},
- /* GPS sleep */
- {70, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
- | FCH_GPIO_OUTPUT_ENABLE},
- /* MUX for Power Express Eval */
- {116, Function1, FCH_GPIO_PULL_DOWN_ENABLE},
- /* SD power */
- {119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
- | FCH_GPIO_OUTPUT_ENABLE},
- {-1}
-};
-/**
- * Fch Oem setting callback
- *
- * Configure platform specific Hudson device,
- * such as Azalia, SATA, IMC etc.
- */
-AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
+static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
{
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
- if (StdHeader->Func == AMD_INIT_RESET) {
- FCH_RESET_DATA_BLOCK *FchParams_reset =
- (FCH_RESET_DATA_BLOCK *)FchData;
- printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- FchParams_reset->FchReset.SataEnable = hudson_sata_enable();
- FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();
- FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
- } else if (StdHeader->Func == AMD_INIT_ENV) {
+ if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
@@ -119,8 +54,25 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FchParams_env->Sata.SataIdeMode = TRUE;
break;
}
+ printk(BIOS_DEBUG, "Done\n");
}
- printk(BIOS_DEBUG, "Done\n");
return AGESA_SUCCESS;
}
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
+ {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
+ {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
+ {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
+ {AGESA_READ_SPD, agesa_ReadSpd },
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_FCH_OEM_CALLOUT, fch_initenv },
+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
+};
+
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc
index ba5e3776fa..4c637bbfbf 100644
--- a/src/mainboard/amd/gardenia/Makefile.inc
+++ b/src/mainboard/amd/gardenia/Makefile.inc
@@ -13,6 +13,9 @@
# GNU General Public License for more details.
#
+bootblock-y += bootblock/BiosCallOuts.c
+bootblock-y += bootblock/OemCustomize.c
+
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c
index 3a34761e50..3893e5dbcb 100644
--- a/src/mainboard/amd/gardenia/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/OemCustomize.c
@@ -18,142 +18,6 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
-/* Port descriptor list for Gardenia Rev. B */
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
- /* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
- PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
- 2, 1,
- HotplugDisabled,
- PcieGenMaxSupported,
- PcieGenMaxSupported,
- AspmL0sL1, 0x04, 0)
- },
- /* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 1),
- PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
- 2, 2,
- HotplugDisabled,
- PcieGenMaxSupported,
- PcieGenMaxSupported,
- AspmL0sL1, 0x17, 0)
- },
- /* Disable M.2 x1 on lane 1, D2F3 */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
- PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
- 2, 3,
- HotplugDisabled,
- PcieGenMaxSupported,
- PcieGenMaxSupported,
- AspmL0sL1, 0x17, 0)
- },
- /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
- PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
- 2, 4,
- HotplugDisabled,
- PcieGenMaxSupported,
- PcieGenMaxSupported,
- AspmL0sL1, 0x13, 0)
- },
- /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */
- {
- DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
- PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
- 2, 5,
- HotplugDisabled,
- PcieGenMaxSupported,
- PcieGenMaxSupported,
- AspmL0sL1, 0x16, 0)
- },
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
- /* DDI0 - eDP */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
- },
- /* DDI1 - DP */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
- },
- /* DDI2 - HDMI */
- {
- DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
- },
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
- .Flags = DESCRIPTOR_TERMINATE_LIST,
- .SocketId = 0,
- .PciePortList = PortList,
- .DdiLinkList = DdiList
-};
-
-static const UINT32 AzaliaCodecAlc286Table[] = {
- 0x00172051, 0x001721C7, 0x00172222, 0x00172310,
- 0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,
- 0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,
- 0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40,
- 0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90,
- 0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41,
- 0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04,
- 0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41,
- 0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41,
- 0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40,
- 0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04,
- 0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04,
- 0x02050071, 0x02040014, 0x02050010, 0x02040C22,
- 0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50,
- 0x0205002D, 0x02041020, 0x02050020, 0x02040000,
- 0x02050019, 0x02040817, 0x02050035, 0x02041AA5,
- 0x02050063, 0x02042906, 0x02050063, 0x02042906,
- 0xffffffff
-};
-
-CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {
- { (UINT32) 0x10ec0286, AzaliaCodecAlc286Table},
- { (UINT32) 0x0FFFFFFFF, (UINT32 *)0x0FFFFFFFF}
-};
-
-/*---------------------------------------------------------------------------*/
-/**
- * OemCustomizeInitEarly
- *
- * Description:
- * This is the stub function will call the host environment through the
- * binary block interface (call-out port) to provide a user hook opportunity
- *
- * Parameters:
- * @param[in] **PeiServices
- * @param[in] *InitEarly
- *
- * @retval VOID
- *
- **/
-/*---------------------------------------------------------------------------*/
-VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
-{
- InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
- InitEarly->PlatformConfig.AzaliaCodecVerbTable =
- (UINT64)(UINTN)CodecTableList;
-}
-
static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
new file mode 100644
index 0000000000..a54078a283
--- /dev/null
+++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <AGESA.h>
+#include <BiosCallOuts.h>
+#include <FchPlatform.h>
+#include <soc/hudson.h>
+#include <stdlib.h>
+
+static const GPIO_CONTROL oem_gardenia_gpio[] = {
+ /* BT radio disable */
+ {14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+ /* NFC PU */
+ {64, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+ /* NFC wake */
+ {65, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+ /* Webcam */
+ {66, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+ /* PCIe presence detect */
+ {69, Function0, FCH_GPIO_PULL_UP_ENABLE},
+ /* GPS sleep */
+ {70, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+ /* MUX for Power Express Eval */
+ {116, Function1, FCH_GPIO_PULL_DOWN_ENABLE},
+ /* SD power */
+ {119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+ | FCH_GPIO_OUTPUT_ENABLE},
+ {-1}
+};
+
+static AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
+{
+ AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
+
+ if (StdHeader->Func == AMD_INIT_RESET) {
+ FCH_RESET_DATA_BLOCK *FchParams_reset;
+ FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+ FchParams_reset->FchReset.SataEnable = hudson_sata_enable();
+ FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();
+ FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
+ printk(BIOS_DEBUG, "Done\n");
+ }
+
+ return AGESA_SUCCESS;
+}
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
+ {AGESA_FCH_OEM_CALLOUT, fch_initreset },
+};
+
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
diff --git a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
new file mode 100644
index 0000000000..5c16c39d6b
--- /dev/null
+++ b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <agesawrapper.h>
+#include <PlatformMemoryConfiguration.h>
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+
+/* Port descriptor list for Gardenia Rev. B */
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+ /* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+ 2, 1,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmL0sL1, 0x04, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+ 2, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmL0sL1, 0x17, 0)
+ },
+ /* Disable M.2 x1 on lane 1, D2F3 */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
+ 2, 3,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmL0sL1, 0x17, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+ 2, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmL0sL1, 0x13, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+ 2, 5,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmL0sL1, 0x16, 0)
+ },
+};
+
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+ /* DDI0 - eDP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
+ },
+ /* DDI1 - DP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+ },
+ /* DDI2 - HDMI */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList
+};
+
+static const UINT32 AzaliaCodecAlc286Table[] = {
+ 0x00172051, 0x001721C7, 0x00172222, 0x00172310,
+ 0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,
+ 0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,
+ 0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40,
+ 0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90,
+ 0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41,
+ 0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04,
+ 0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41,
+ 0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41,
+ 0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40,
+ 0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04,
+ 0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04,
+ 0x02050071, 0x02040014, 0x02050010, 0x02040C22,
+ 0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50,
+ 0x0205002D, 0x02041020, 0x02050020, 0x02040000,
+ 0x02050019, 0x02040817, 0x02050035, 0x02041AA5,
+ 0x02050063, 0x02042906, 0x02050063, 0x02042906,
+ 0xffffffff
+};
+
+static CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {
+ { 0x10ec0286, AzaliaCodecAlc286Table},
+ { 0x0FFFFFFFF, (void *)0x0FFFFFFFF}
+};
+
+/*---------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This is the stub function will call the host environment through the
+ * binary block interface (call-out port) to provide a user hook opportunity.
+ *
+ * Parameters:
+ * @param[in] **PeiServices
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------*/
+VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+ InitEarly->PlatformConfig.AzaliaCodecVerbTable =
+ (uint64_t)(uintptr_t)CodecTableList;
+}
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index 39422a10de..9a7f168f25 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -12,72 +12,3 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <cbmem.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/bist.h>
-#include <cpu/amd/car.h>
-#include <agesawrapper.h>
-#include <agesawrapper_call.h>
-#include <soc/hudson.h>
-#include <amdblocks/psp.h>
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- u32 val;
-
- amd_initmmio();
- hudson_lpc_port80();
- hudson_lpc_decode();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- if (IS_ENABLED(CONFIG_STONEYRIDGE_UART))
- configure_hudson_uart();
-
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- /* Mask bit 31. One result of Silicon Observation */
- report_bist_failure(bist & 0x7FFFFFFF);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- post_code(0x37);
- AGESAWRAPPER(amdinitreset);
- post_code(0x38);
- printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
-
- post_code(0x39);
- AGESAWRAPPER(amdinitearly);
-
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
-
- post_code(0x41);
- psp_notify_dram();
-
- post_code(0x42);
- cbmem_initialize_empty();
-
- post_code(0x43);
- AGESAWRAPPER(amdinitenv);
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
-}