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authorScott Duplichan <scott@notabs.org>2011-05-15 21:48:22 +0000
committerMarc Jones <marc.jones@amd.com>2011-05-15 21:48:22 +0000
commite73fc20886e094149f44f9306ef15971154f59ee (patch)
tree2505f1a8dd95357ca1e2306a10866fbdc5a24b23 /src/mainboard/amd
parent9ab3c6c3a95d0dd438e9b105a22a45f021a24aec (diff)
downloadcoreboot-e73fc20886e094149f44f9306ef15971154f59ee.tar.xz
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/persimmon/romstage.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index aff41939a2..51e7a8df1f 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -47,6 +47,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
u8 reg8;
+ // early enable of SPI 33 MHz fast mode read
+ if (boot_cpu())
+ {
+ volatile u32 *spiBase = (void *) 0xa0000000;
+ u32 save;
+ __outdword (0xcf8, 0x8000a3a0);
+ save = __indword (0xcfc);
+ __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
+ spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
+ spiBase [0] |= 1 << 18; // fast read enable
+ __outdword (0xcfc, save); // clear temp base
+ }
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_poweron_init();