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authorSteven Sherk <steven.sherk@se-eng.com>2013-05-22 13:49:18 -0600
committerRonald G. Minnich <rminnich@gmail.com>2013-05-31 18:17:49 +0200
commit474eeedbc85545fce4e5feba21e79bd043d2f858 (patch)
tree22efd0bd0f8a0e0553f5d1b2cefb2834f5ec18f4 /src/mainboard/amd
parent0390112407c042211428a2aee1ab77422caab338 (diff)
downloadcoreboot-474eeedbc85545fce4e5feba21e79bd043d2f858.tar.xz
AMD Trinity boards: Add reserved memory area for SPI base address in ACPI
- SPI controller base address gets overwritten by SD controller under Linux. - Reason for overwrite is the SPI base address isn't in a standard BAR and doesn't get automatically reserved. Solution is to add it as a reserved memory area in ACPI. - This issue was found on the ASUS F2A85-M platform. Currently a workaround on this platform was made as part of: http://review.coreboot.org/#/c/3167/3 - Once approved a follow-on patch for other southbridges using a non-standard BAR for the spi controller. Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/3270 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/parmer/dsdt.asl27
-rw-r--r--src/mainboard/amd/thatcher/dsdt.asl27
2 files changed, 54 insertions, 0 deletions
diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl
index 3e408c8e78..e36965efae 100644
--- a/src/mainboard/amd/parmer/dsdt.asl
+++ b/src/mainboard/amd/parmer/dsdt.asl
@@ -1251,6 +1251,33 @@ DefinitionBlock (
* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
} */ /* End Method(_SB.SBRDG._INI) */
+ OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
+ Field(CFG,DWordAcc,NoLock,Preserve){
+ Offset(0xA0),
+ BAR,32} // SPI Controller Base Address Register (Index 0xA0)
+
+ Device(LDRC) // LPC device: Resource consumption
+ {
+ Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources
+ Name (CRS, ResourceTemplate () // Current Motherboard resources
+ {
+ Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address
+ 0x00000000, // Address Base
+ 0x00000000, // Address Length
+ BAR0 // Descriptor Name
+ )
+ })
+
+ Method(_CRS,0,NotSerialized)
+ {
+ CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
+ CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length
+ Store(BAR,SPIB) // SPI base address mapped
+ Store(0x1000,SPIL) // 4k space mapped
+ Return(CRS)
+ }
+ }
+
/* Real Time Clock Device */
Device(RTC0) {
Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl
index faf3ad74a7..7f08bbb350 100644
--- a/src/mainboard/amd/thatcher/dsdt.asl
+++ b/src/mainboard/amd/thatcher/dsdt.asl
@@ -1242,6 +1242,33 @@ DefinitionBlock (
* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
} */ /* End Method(_SB.SBRDG._INI) */
+ OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
+ Field(CFG,DWordAcc,NoLock,Preserve){
+ Offset(0xA0),
+ BAR,32} // SPI Controller Base Address Register (Index 0xA0)
+
+ Device(LDRC) // LPC device: Resource consumption
+ {
+ Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources
+ Name (CRS, ResourceTemplate () // Current Motherboard resources
+ {
+ Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address
+ 0x00000000, // Address Base
+ 0x00000000, // Address Length
+ BAR0 // Descriptor Name
+ )
+ })
+
+ Method(_CRS,0,NotSerialized)
+ {
+ CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
+ CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length
+ Store(BAR,SPIB) // SPI base address mapped
+ Store(0x1000,SPIL) // 4k space mapped
+ Return(CRS)
+ }
+ }
+
/* Real Time Clock Device */
Device(RTC0) {
Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */