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| author | Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> | 2021-05-03 06:52:53 -0700 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2021-05-06 14:27:53 +0000 |
| commit | 4e3658fd57bd39acf66cd8061b22c3533068feab (patch) | |
| tree | a9a248a65b65e3bf797f01d857074d4bee3b2677 /src/mainboard/amd | |
| parent | a1c4ad38d525d019d52fc0d421ae695e9eb8b01a (diff) | |
| download | coreboot-4e3658fd57bd39acf66cd8061b22c3533068feab.tar.xz | |
mb/amd/majolica: Enable S0i3 by default
Set s0ix_enable to true.
BUG=b:178728116
TEST=Cold boot and perform a cycle of S0i3.
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/majolica/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index fec764e0a5..502ae251e0 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -14,6 +14,8 @@ chip soc/amd/cezanne .flash_ch_en = 0, }" + register "s0ix_enable" = "true" + device domain 0 on device ref gpp_gfx_bridge_0 on end # MXM device ref gpp_bridge_0 on end # NVMe |