diff options
| author | Nils Jacobs <njacobs8@hetnet.nl> | 2010-12-29 21:12:10 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2010-12-29 21:12:10 +0000 |
| commit | 84be0f59b7158d5d60e1d7d61786d0a6e449d682 (patch) | |
| tree | 8a789558b684762746f8c8273ae309571d89a0de /src/mainboard/amd | |
| parent | cdcf9833e804f3549257c3d071862a0e6ac4bfac (diff) | |
| download | coreboot-84be0f59b7158d5d60e1d7d61786d0a6e449d682.tar.xz | |
-Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)
to FG (FooGlue). As the GX2 has no VIP port.
-Change the Memmory setup MSR register names so they correspond better to the
databook. (Part1)
This is less confusing for beginners.
-Add a MSR printing function to northbridge.c like in the Geode LX code.
-Remove the AES register names.(GX2 has no AES registers)
-Delete some unused code.
-Clean up GX2 northbridge code to match Geode LX code.
-Add missing copyright header to northbridge.c.
-Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/rumba/irq_tables.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/amd/rumba/irq_tables.c b/src/mainboard/amd/rumba/irq_tables.c index adbe0d1acb..386e12e10a 100644 --- a/src/mainboard/amd/rumba/irq_tables.c +++ b/src/mainboard/amd/rumba/irq_tables.c @@ -7,6 +7,24 @@ #include <arch/pirq_routing.h> +/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 5 +#define PIRQC 10 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ |