semi working with random 1 bit error

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 32 insertions, 2 deletions

diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index b15937126b..08fe8ed6ca 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -60,8 +60,36 @@ static void msr_init(void)
 
 }
 
-static pll_reset(void)
+static void pll_reset(void)
 {
+	msr_t msr;
+
+	msr = rdmsr(0x4c000014);
+	print_debug("CGLP_SYS_RSTPLL ");
+	print_debug_hex32(msr.hi);
+	print_debug(":");
+	print_debug_hex32(msr.lo);
+	print_debug("\n\r");
+
+	if ((msr.lo >> 26) & 0x3F) {
+		print_debug("reboot from BIOS reset\n\r");
+		return;
+	}
+	print_debug("prgramming PLL\n\r");
+	
+	msr.hi = 0x00000019;
+	msr.lo = 0x06de0378;
+	wrmsr(0x4c000014, msr);
+	msr.lo |= ((0xde << 16) | (1 << 26));
+	wrmsr(0x4c000014, msr);
+
+	print_debug("Reset PLL\n\r");
+
+	msr.lo |= ((1<<14) |(1<<13) | (1<<0));
+	wrmsr(0x4c000014,msr);
+
+	print_debug("should not be here\n\r");
+
 
 }
 static void main(unsigned long bist)
@@ -76,7 +104,9 @@ static void main(unsigned long bist)
 	uart_init();
 	console_init();
 
-	print_err("hi\n");
+	print_err("hi\n\r");
+
+	pll_reset();
 
 	/* Halt if there was a built in self test failure */
 	//report_bist_failure(bist);