Clean up #ifs

Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +

Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +

Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +

Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +

(and some manual changes to fix false positives)

Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>

52 files changed, 79 insertions, 79 deletions

diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c
index e53aef5109..41a2fe7676 100644
--- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 #include <cpu/amd/amdfam10_sysconf.h>
@@ -138,7 +138,7 @@ void get_bus_conf(void)
 
 	/* I/O APICs:   APIC ID Version State   Address */
 	bus_isa = 10;
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(1);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c
index 1fd0eebf0f..241d9057c0 100644
--- a/src/mainboard/amd/bimini_fam10/mainboard.c
+++ b/src/mainboard/amd/bimini_fam10/mainboard.c
@@ -134,7 +134,7 @@ static void bimini_enable(device_t dev)
 
 	printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev);
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
@@ -184,7 +184,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
 		    uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c
index ae81411e2e..ec60b35a1d 100644
--- a/src/mainboard/amd/bimini_fam10/mptable.c
+++ b/src/mainboard/amd/bimini_fam10/mptable.c
@@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
 #else
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 732e03322e..5980ca2a2e 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();
diff --git a/src/mainboard/amd/dbm690t/get_bus_conf.c b/src/mainboard/amd/dbm690t/get_bus_conf.c
index 2b0fca7abf..d4152a1314 100644
--- a/src/mainboard/amd/dbm690t/get_bus_conf.c
+++ b/src/mainboard/amd/dbm690t/get_bus_conf.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 
@@ -107,7 +107,7 @@ void get_bus_conf(void)
 	}
 
 	/* I/O APICs:   APIC ID Version State   Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(1);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c
index 2f54bfdc68..8841291c92 100644
--- a/src/mainboard/amd/dbm690t/mainboard.c
+++ b/src/mainboard/amd/dbm690t/mainboard.c
@@ -187,7 +187,7 @@ static void dbm690t_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev);
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
@@ -238,7 +238,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
 	uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
index cf98ae30d9..f34918f363 100644
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ b/src/mainboard/amd/dbm690t/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
 #else
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 66637a8b72..459aa47e90 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	setup_coherent_ht_domain();
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched */
 	wait_all_core0_started();
 	start_other_cores();
diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c
index 9d10390e83..360e1df447 100644
--- a/src/mainboard/amd/dinar/mainboard.c
+++ b/src/mainboard/amd/dinar/mainboard.c
@@ -75,7 +75,7 @@ uint64_t uma_memory_base, uma_memory_size;
 static void dinar_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 	uint32_t sys_mem;
 
@@ -124,7 +124,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
 	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
 			uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h
index a4f4e1a655..aaab1f3b5f 100644
--- a/src/mainboard/amd/dinar/rd890_cfg.h
+++ b/src/mainboard/amd/dinar/rd890_cfg.h
@@ -32,10 +32,10 @@
  * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
  */
 #ifndef DEFAULT_HT_PATH
-#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
+#if CONFIG_CPU_AMD_AGESA_FAMILY10
 #define DEFAULT_HT_PATH		{0x0, 0x3}
 #endif
-#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
+#if CONFIG_CPU_AMD_AGESA_FAMILY15
 #define DEFAULT_HT_PATH		{0x0, 0x1}
 #endif
 #endif
diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h
index b405f0e78e..038e7e7d8d 100644
--- a/src/mainboard/amd/dinar/sb700_cfg.h
+++ b/src/mainboard/amd/dinar/sb700_cfg.h
@@ -40,7 +40,7 @@
  * before AGESA module get call.
  */
 #ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
 #define BIOS_SIZE BIOS_SIZE_1M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
 #define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index 17c985de0d..d35b1757f9 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -80,7 +80,7 @@ static void inagua_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 	uint32_t sys_mem;
 
@@ -128,7 +128,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
 	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
 			uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index b5a507f248..393eb9e03b 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
 #else
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
index 2a3342c553..dd0251ffc2 100644
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -37,7 +37,7 @@
  * before AGESA module get call.
  */
 #ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
 #define BIOS_SIZE BIOS_SIZE_1M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
 #define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/amd/mahogany/get_bus_conf.c b/src/mainboard/amd/mahogany/get_bus_conf.c
index bed760618e..149e163574 100644
--- a/src/mainboard/amd/mahogany/get_bus_conf.c
+++ b/src/mainboard/amd/mahogany/get_bus_conf.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 
@@ -107,7 +107,7 @@ void get_bus_conf(void)
 	}
 
 	/* I/O APICs:   APIC ID Version State   Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(1);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index 0ccef102f3..989070cb03 100644
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -105,7 +105,7 @@ static void mahogany_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
@@ -154,7 +154,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
 		    uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
index dabd2ed574..376e043530 100644
--- a/src/mainboard/amd/mahogany/mptable.c
+++ b/src/mainboard/amd/mahogany/mptable.c
@@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
 #else
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 104652a76f..9d913e977a 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	setup_coherent_ht_domain();
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched */
 	wait_all_core0_started();
 	start_other_cores();
diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
index b169775456..563a87efd5 100644
--- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 
@@ -107,7 +107,7 @@ void get_bus_conf(void)
 	}
 
 	/* I/O APICs:   APIC ID Version State   Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(1);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index 2cbeaf127b..1f1941b02d 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -106,7 +106,7 @@ static void mahogany_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
@@ -155,7 +155,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
 		    uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index c56952e934..d69c7b78a6 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
 #else
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index dce9baabd3..d48b69d24a 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
- #if CONFIG_LOGICAL_CPUS==1
+ #if CONFIG_LOGICAL_CPUS
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();
diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index e60673ec9b..0d63abb02b 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
@@ -515,7 +515,7 @@ agesawrapper_amdinitlate (
 	return (UINT32)Status;
 }
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 UINT32
 agesawrapper_amdinitresume (
   VOID
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index 4c094aecae..1d5842acfd 100644
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -51,7 +51,7 @@ u32 sbdn_sb800;
 
 static u32 get_bus_conf_done = 0;
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 extern u8 acpi_slp_type;
 #endif
 
@@ -83,7 +83,7 @@ void get_bus_conf(void)
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 	if (acpi_slp_type != 3) {
 		status = agesawrapper_amdinitlate();
 		if(status)
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index 9a8428e25b..76a9ae6ae4 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -63,11 +63,11 @@ static void persimmon_enable(device_t dev)
  * The mainboard is the first place that we get control in ramstage. Check
  * for S3 resume and call the approriate AGESA/CIMx resume functions.
  */
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 	acpi_slp_type = acpi_get_sleep_type();
 #endif
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 	uint32_t sys_mem;
 
@@ -113,7 +113,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
 			uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 61ddef184e..d0c31f00d9 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
 #else
diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
index 97aa47e2e2..db3fc158a1 100644
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ b/src/mainboard/amd/persimmon/platform_cfg.h
@@ -37,7 +37,7 @@
  * before AGESA module get call.
  */
 #ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
   #define BIOS_SIZE BIOS_SIZE_1M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
   #define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 55d05168f6..56a67886c8 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -51,7 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 	void *resume_backup_memory;
 #endif
 
@@ -107,7 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	else
 		printk(BIOS_DEBUG, "passed.\n");
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 	if (!acpi_is_wakeup_early()) { /* Check for S3 resume */
 #endif
 		post_code(0x40);
@@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		else
 			printk(BIOS_DEBUG, "passed.\n");
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 	} else { 			/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
diff --git a/src/mainboard/amd/pistachio/get_bus_conf.c b/src/mainboard/amd/pistachio/get_bus_conf.c
index 2b0fca7abf..d4152a1314 100644
--- a/src/mainboard/amd/pistachio/get_bus_conf.c
+++ b/src/mainboard/amd/pistachio/get_bus_conf.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 
@@ -107,7 +107,7 @@ void get_bus_conf(void)
 	}
 
 	/* I/O APICs:   APIC ID Version State   Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(1);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c
index d1d9a849fc..e5d0efa807 100644
--- a/src/mainboard/amd/pistachio/mainboard.c
+++ b/src/mainboard/amd/pistachio/mainboard.c
@@ -257,7 +257,7 @@ static void pistachio_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev);
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
@@ -308,7 +308,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
 	uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
index cf98ae30d9..f34918f363 100644
--- a/src/mainboard/amd/pistachio/mptable.c
+++ b/src/mainboard/amd/pistachio/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
 #else
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 5d6e7a848b..45c94c8aba 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -101,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	setup_coherent_ht_domain();
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched */
 	wait_all_core0_started();
 	start_other_cores();
diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
index 36b5776c5e..d4f44c0d93 100644
--- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
@@ -3,7 +3,7 @@
 #include <device/pci_ids.h>
 #include <string.h>
 #include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 
@@ -192,7 +192,7 @@ void get_bus_conf(void)
 
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(3);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 4214408b86..866875dc63 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -4,7 +4,7 @@
 #include <device/pci.h>
 #include <string.h>
 #include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 #include <cpu/amd/amdk8_sysconf.h>
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 8378ca4abe..2524e522a2 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -1,4 +1,4 @@
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	setup_coherent_ht_domain(); // routing table and start other core0
 
 	wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
         // It is said that we should start core1 after all core0 launched
 	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 	 * So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
index b595473304..da7efe6e8d 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
@@ -22,7 +22,7 @@
 #include <device/pci_ids.h>
 #include <string.h>
 #include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index e90b348acb..d19b3c66f6 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -23,7 +23,7 @@
 #include <device/pci.h>
 #include <string.h>
 #include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 #include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 29b00b27d4..09447a63c1 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
- #if CONFIG_LOGICAL_CPUS==1
+ #if CONFIG_LOGICAL_CPUS
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index 990c8b9674..ed65b34622 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -82,7 +82,7 @@ static void southstation_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 	uint32_t sys_mem;
 
@@ -129,7 +129,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
 		    uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 99004b3f2e..ba73ce0e51 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
   /* PCI interrupts are level triggered, and are
    * associated with a specific bus/device/function tuple.
    */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
 #else
diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h
index 66aab8bf4b..1c8506b029 100644
--- a/src/mainboard/amd/south_station/platform_cfg.h
+++ b/src/mainboard/amd/south_station/platform_cfg.h
@@ -37,7 +37,7 @@
  * before AGESA module get call.
  */
 #ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
   #define BIOS_SIZE BIOS_SIZE_1M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
   #define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
index b169775456..563a87efd5 100644
--- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 
@@ -107,7 +107,7 @@ void get_bus_conf(void)
 	}
 
 	/* I/O APICs:   APIC ID Version State   Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(1);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index 357bdac230..e2ef3f96bb 100644
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -281,7 +281,7 @@ static void tilapia_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev);
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
@@ -331,7 +331,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
 		    uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index 4a276fb0c3..d7951cf8be 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
 #else
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index f316395e27..9919cce880 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();
diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h
index 037ce94ef8..4acc136605 100644
--- a/src/mainboard/amd/torpedo/Oem.h
+++ b/src/mainboard/amd/torpedo/Oem.h
@@ -20,7 +20,7 @@
 	#define BIOS_SIZE                      0x04   //04 - 1MB
 #endif
 #define LEGACY_FREE                    0x00
-#if CONFIG_ONBOARD_USB30 == 0
+#if !CONFIG_ONBOARD_USB30
   #define XHCI_SUPPORT                 0x01
 #endif
 
diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c
index 2152153936..7248bfb27f 100644
--- a/src/mainboard/amd/torpedo/mainboard.c
+++ b/src/mainboard/amd/torpedo/mainboard.c
@@ -58,7 +58,7 @@ uint64_t uma_memory_base, uma_memory_size;
 static void torpedo_enable(device_t dev)
 {
   printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
   msr_t msr, msr2;
   uint32_t sys_mem;
 
@@ -107,7 +107,7 @@ int add_mainboard_resources(struct lb_memory *mem)
   /* UMA is removed from system memory in the northbridge code, but
    * in some circumstances we want the memory mentioned as reserved.
    */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
   printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
         uma_memory_base, uma_memory_size);
   lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 936a41717c..95137415b1 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v)
   /* PCI interrupts are level triggered, and are
    * associated with a specific bus/device/function tuple.
    */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, int_sign, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
 #else
diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h
index cf31c6affd..a6d02e8b78 100644
--- a/src/mainboard/amd/torpedo/platform_cfg.h
+++ b/src/mainboard/amd/torpedo/platform_cfg.h
@@ -39,7 +39,7 @@
 #define BIOS_SIZE_4M			3
 #define BIOS_SIZE_8M			7
 
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
   #define BIOS_SIZE BIOS_SIZE_1M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
   #define BIOS_SIZE BIOS_SIZE_2M
@@ -311,7 +311,7 @@
 #define INCHIP_USB_CINFIG          0x7F
 #define INCHIP_USB_OHCI1_CINFIG    0x01
 #define INCHIP_USB_OHCI2_CINFIG    0x01
-#if CONFIG_ONBOARD_USB30 == 1
+#if CONFIG_ONBOARD_USB30
 #define INCHIP_USB_OHCI3_CINFIG    0x00
 #else
 #define INCHIP_USB_OHCI3_CINFIG    0x01
@@ -985,7 +985,7 @@
  *    @li <b>0</b> - Disable
  *    @li <b>1</b> - Enable
  */
-#if CONFIG_ONBOARD_USB30 == 1
+#if CONFIG_ONBOARD_USB30
 	#define SB_XHCI_SWITCH 0
 #else
 #define SB_XHCI_SWITCH 1
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
index 800d64d58c..c5b481d5f0 100644
--- a/src/mainboard/amd/union_station/mainboard.c
+++ b/src/mainboard/amd/union_station/mainboard.c
@@ -56,7 +56,7 @@ static void unionstation_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 	uint32_t sys_mem;
 
@@ -103,7 +103,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
  	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
 		    uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 99004b3f2e..ba73ce0e51 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
   /* PCI interrupts are level triggered, and are
    * associated with a specific bus/device/function tuple.
    */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
 #else
diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h
index 66aab8bf4b..1c8506b029 100644
--- a/src/mainboard/amd/union_station/platform_cfg.h
+++ b/src/mainboard/amd/union_station/platform_cfg.h
@@ -37,7 +37,7 @@
  * before AGESA module get call.
  */
 #ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
   #define BIOS_SIZE BIOS_SIZE_1M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
   #define BIOS_SIZE BIOS_SIZE_2M