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authorMyles Watson <mylesgw@gmail.com>2010-04-15 05:19:29 +0000
committerMyles Watson <mylesgw@gmail.com>2010-04-15 05:19:29 +0000
commit075fbe820127c454a6854b87c277a2ca30dee1c2 (patch)
treeabc89718ed34b04febd7d6beae8e57cd54f3f5b0 /src/mainboard/amd
parent07ef092ef228b4cc7c85f375c0390acc901b5181 (diff)
downloadcoreboot-075fbe820127c454a6854b87c277a2ca30dee1c2.tar.xz
Remove a few more warnings from fam10.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/mahogany_fam10/romstage.c4
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/romstage.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 1f5366912d..17a0fd606f 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -93,6 +93,8 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/fidvid.c"
@@ -100,8 +102,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "southbridge/amd/sb700/sb700_early_setup.c"
//#include "spd_addr.h"
-#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
#define RC00 0
#define RC01 1
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 316e257dc1..b571d37c40 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -115,6 +115,8 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "cpu/amd/model_10xxx/fidvid.c"
@@ -122,8 +124,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c"
#include "spd_addr.h"
-#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{