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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-26 22:35:11 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-26 22:35:11 +0000
commit1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (patch)
treeb9e14e6c08cdcc52b4fa00cfe730fffa55ae137e /src/mainboard/amd
parentdf323fcefd6020f8f418a13d65a075d282eed3de (diff)
downloadcoreboot-1f7d3c5672ec90f8d71907b1a07c8a87fa461047.tar.xz
AMD-8111: Add TINY_BOOTBLOCK support.
Also, add missing license header to amd8111_enable_rom.c, add some more code comments and use PCI IDs from pci_ids.h instead of hardcoding. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/serengeti_cheetah/romstage.c2
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/romstage.c4
2 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 24a6525e58..ee78f31c5c 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -85,7 +85,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#define RC0 ((1<<0)<<8)
@@ -126,7 +125,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
- amd8111_enable_rom();
}
if (bist == 0)
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 5274ef2e4a..2124c284c9 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -89,7 +89,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static const u8 spd_addr[] = {
@@ -197,9 +196,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
- amd8111_enable_rom();
}
post_code(0x30);