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authorKerry She <shekairui@gmail.com>2011-06-24 22:52:15 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2011-06-29 00:22:16 +0200
commit3e706b63c03b4d1d64a21f4c26eaa12fc88cb1f8 (patch)
tree534b511aee308d98f3d1be3946ab1cd3383637a0 /src/mainboard/amd
parent770b877796c1b4632b00191458dbc153226c6bee (diff)
downloadcoreboot-3e706b63c03b4d1d64a21f4c26eaa12fc88cb1f8.tar.xz
amd southbirdge sb800 wrapper, pci bridge fix
sb800 pci bridge SHOULD enabled by default according to the chipset document, but actually not enabled on some mainboard. enable sb800 pci bridge when told to enable in devicetree.cb. tested on ibase persimmon mainboard. Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3 Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/63 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/inagua/devicetree.cb2
-rw-r--r--src/mainboard/amd/persimmon/devicetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 67be34e8be..82658cffbc 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -65,7 +65,7 @@ chip northbridge/amd/agesa/family14/root_complex
end
end # kbc1100
end #LPC
- device pci 14.4 on end # PCI 0x4384
+ device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 15.0 on end # PCIe PortA
device pci 15.1 on end # PCIe PortB
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index a6763884c7..3cb8d1e342 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -81,7 +81,7 @@ chip northbridge/amd/agesa/family14/root_complex
end
end # f81865f
end #LPC
- device pci 14.4 on end # PCI 0x4384
+ device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB