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authorMarc Jones <marc.jones@se-eng.com>2012-02-21 17:53:13 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2012-02-22 11:35:17 +0100
commitfff8cdfcdeedb3723bd9dba66e19ae1a56ba9c8f (patch)
tree1589a3135ec4dbe3e3166350969357a154f536c1 /src/mainboard/amd
parent0864016b0d5d9d7e54f120873282967759886d95 (diff)
downloadcoreboot-fff8cdfcdeedb3723bd9dba66e19ae1a56ba9c8f.tar.xz
Remove old AMD fam10 fixme comment
The family10 code had a very slow decompress before the cache settings were fixed. This has been fixed for some time. Remove all the old messages from the serial stream. Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/672 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/mahogany_fam10/romstage.c1
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/romstage.c1
-rw-r--r--src/mainboard/amd/tilapia_fam10/romstage.c1
3 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 04a9e45a57..dce9baabd3 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -220,7 +220,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index b41230dece..29b00b27d4 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -331,7 +331,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 52cab42eb4..f316395e27 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -220,7 +220,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}