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| author | WANG Siyuan <wangsiyuanbuaa@gmail.com> | 2014-12-17 17:30:54 +0800 |
|---|---|---|
| committer | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2014-12-18 19:26:16 +0100 |
| commit | 0664d22337e4bff8f19bed75d091e3500990fafb (patch) | |
| tree | 9819cc8316066d6b782c9d3c37345b9a9ba3e45d /src/mainboard/amd | |
| parent | 41877d8690c79ce1ff12272d4427e8ff4f5cfc74 (diff) | |
| download | coreboot-0664d22337e4bff8f19bed75d091e3500990fafb.tar.xz | |
amd/olivehillplus/romstage.c: remove not useful variable 'halt'
The variable 'halt' is not useful and results in a compile error
because of:
1b2f2a07 Introduce halt()
build error:
src/mainboard/amd/olivehillplus/romstage.c: In function 'cache_as_ram_main':
src/mainboard/amd/olivehillplus/romstage.c:43:15: error: declaration of 'halt' shadows a global declaration [-Werror=shadow]
In file included from src/include/cpu/x86/lapic.h:6:0,
from src/mainboard/amd/olivehillplus/romstage.c:29:
src/include/halt.h:31:32: error: shadowed declaration is here [-Werror=shadow]
cc1: all warnings being treated as errors
make: *** [build/mainboard/amd/olivehillplus/romstage.pre.inc] Error 1
Change-Id: Id67a0dcb192fb6478115e489f46bfb07021afd90
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/7847
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/olivehillplus/romstage.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 367fa6a776..f603d738c5 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -40,7 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - volatile int halt = 0; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for @@ -64,9 +63,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); } - if(boot_cpu()) { - while(halt); - } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); |