make solo target build again

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 100 insertions, 194 deletions

diff --git a/src/mainboard/amd/solo/auto.c b/src/mainboard/amd/solo/auto.c
index bb1cd753fe..2b3ef3210b 100644
--- a/src/mainboard/amd/solo/auto.c
+++ b/src/mainboard/amd/solo/auto.c
@@ -1,19 +1,30 @@
 #define ASSEMBLY 1
+#define MAXIMUM_CONSOLE_LOGLEVEL 9
+#define DEFAULT_CONSOLE_LOGLEVEL 9
+
 #include <stdint.h>
 #include <device/pci_def.h>
-#include "arch/romcc_io.h"
+#include <cpu/p6/apic.h>
+#include <arch/io.h>
+#include <device/pnp.h>
+#include <arch/romcc_io.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/k8/apic_timer.c"
+#include "lib/delay.c"
+#include "cpu/p6/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "debug.c"
 
-static void memreset_setup(const struct mem_controller *ctrl)
+static void memreset_setup(void)
 {
 }
 
-static void memreset(const struct mem_controller *ctrl)
+static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
 
@@ -22,7 +33,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
 	/* since the AMD Solo is a UP only machine, we can 
 	 * always return the default row entry value
 	 */
-        return 0x00010101; /* default row entry */
+	return 0x00010101; /* default row entry */
 }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
@@ -30,215 +41,95 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
+#include "northbridge/amd/amdk8/cpu_ldtstop.c"
+#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
-#define NODE_ID		0x60
-#define	HT_INIT_CONTROL 0x6c
-
-#define HTIC_ColdR_Detect  (1<<4)
-#define HTIC_BIOSR_Detect  (1<<5)
-#define HTIC_INIT_Detect   (1<<6)
-
-static int boot_cpu(void)
+static void enable_lapic(void)
 {
-	volatile unsigned long *local_apic;
-	unsigned long apic_id;
-	int bsp;
+
 	msr_t msr;
 	msr = rdmsr(0x1b);
-	bsp = !!(msr.lo & (1 << 8));
-	if (bsp) {
-		print_debug("Bootstrap processor\r\n");
-	} else {
-		print_debug("Application processor\r\n");
-	}
-
-	return bsp;
+	msr.hi &= 0xffffff00;
+	msr.lo &= 0x000007ff;
+	msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
+	wrmsr(0x1b, msr);
 }
 
-static int cpu_init_detected(void)
+static void stop_this_cpu(void)
 {
-	unsigned long dcl;
-	int cpu_init;
-
-	unsigned long htic;
-
-	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
-#if 0
-	print_debug("htic: ");
-	print_debug_hex32(htic);
-	print_debug("\r\n");
-
-	if (!(htic & HTIC_ColdR_Detect)) {
-		print_debug("Cold Reset.\r\n");
-	}
-	if ((htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect)) {
-		print_debug("BIOS generated Reset.\r\n");
-	}
-	if (htic & HTIC_INIT_Detect) {
-		print_debug("Init event.\r\n");
+	unsigned apicid;
+	apicid = apic_read(APIC_ID) >> 24;
+
+	/* Send an APIC INIT to myself */
+	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
+	apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
+	/* Wait for the ipi send to finish */
+	apic_wait_icr_idle();
+
+	/* Deassert the APIC INIT */
+	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
+	apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
+	/* Wait for the ipi send to finish */
+	apic_wait_icr_idle();
+
+	/* If I haven't halted spin forever */
+	for(;;) {
+		hlt();
 	}
-#endif
-	cpu_init = (htic & HTIC_INIT_Detect);
-	if (cpu_init) {
-		print_debug("CPU INIT Detected.\r\n");
-	}
-	return cpu_init;
-}
-
-
-static void print_debug_pci_dev(unsigned dev)
-{
-	print_debug("PCI: ");
-	print_debug_hex8((dev >> 16) & 0xff);
-	print_debug_char(':');
-	print_debug_hex8((dev >> 11) & 0x1f);
-	print_debug_char('.');
-	print_debug_hex8((dev >> 8) & 7);
 }
 
-static void print_pci_devices(void)
+static void main(void)
 {
-	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0, 0x1f, 0x7); 
-		dev += PCI_DEV(0,0,1)) {
-		uint32_t id;
-		id = pci_read_config32(dev, PCI_VENDOR_ID);
-		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0x0000)) {
-			continue;
+	/*
+	 * GPIO28 of 8111 will control H0_MEMRESET_L
+	 */
+	static const struct mem_controller cpu[] = {
+		{
+			.node_id = 0,
+			.f0 = PCI_DEV(0, 0x18, 0),
+			.f1 = PCI_DEV(0, 0x18, 1),
+			.f2 = PCI_DEV(0, 0x18, 2),
+			.f3 = PCI_DEV(0, 0x18, 3),
+			.channel0 = { (0xa<<3), (0xa<<3)|1, 0, 0 },
+			.channel1 = { 0, 0, 0, 0 },
 		}
-		print_debug_pci_dev(dev);
-		print_debug("\r\n");
-	}
-}
-
+	};
 
-static void dump_pci_device(unsigned dev)
-{
-	int i;
-	print_debug_pci_dev(dev);
-	print_debug("\r\n");
-	
-	for(i = 0; i <= 255; i++) {
-		unsigned char val;
-		if ((i & 0x0f) == 0) {
-			print_debug_hex8(i);
-			print_debug_char(':');
-		}
-		val = pci_read_config8(dev, i);
-		print_debug_char(' ');
-		print_debug_hex8(val);
-		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
-		}
+	if (cpu_init_detected()) {
+		asm("jmp __cpu_reset");
 	}
-}
 
-static void dump_spd_registers(const struct mem_controller *ctrl)
-{
-	int i;
-	print_debug("\r\n");
-	for(i = 0; i < 4; i++) {
-		unsigned device;
-		device = ctrl->channel0[i];
-		if (device) {
-			int j;
-			print_debug("dimm: "); 
-			print_debug_hex8(i); 
-			print_debug(".0: ");
-			print_debug_hex8(device);
-			for(j = 0; j < 256; j++) {
-				int status;
-				unsigned char byte;
-				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
-					print_debug_hex8(j);
-					print_debug(": ");
-				}
-				status = smbus_read_byte(device, j);
-				if (status < 0) {
-					print_debug("bad device\r\n");
-					break;
-				}
-				byte = status & 0xff;
-				print_debug_hex8(byte);
-				print_debug_char(' ');
-			}
-			print_debug("\r\n");
-		}
-		device = ctrl->channel1[i];
-		if (device) {
-			int j;
-			print_debug("dimm: "); 
-			print_debug_hex8(i); 
-			print_debug(".1: ");
-			print_debug_hex8(device);
-			for(j = 0; j < 256; j++) {
-				int status;
-				unsigned char byte;
-				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
-					print_debug_hex8(j);
-					print_debug(": ");
-				}
-				status = smbus_read_byte(device, j);
-				if (status < 0) {
-					print_debug("bad device\r\n");
-					break;
-				}
-				byte = status & 0xff;
-				print_debug_hex8(byte);
-				print_debug_char(' ');
-			}
-			print_debug("\r\n");
-		}
-	}
-}
+	enable_lapic();
+	init_timer();
 
+	if (!boot_cpu()) {
+		notify_bsp_ap_is_stopped();
+		stop_this_cpu();
+	}
 
-static void main(void)
-{
-	static const struct mem_controller cpu0 = {
-		.f0 = PCI_DEV(0, 0x18, 0),
-		.f1 = PCI_DEV(0, 0x18, 1),
-		.f2 = PCI_DEV(0, 0x18, 2),
-		.f3 = PCI_DEV(0, 0x18, 3),
-		.channel0 = { (0xa << 3), (0xa << 3)|1, 0, 0 },
-		.channel1 = { 0, 0, 0, 0},
-	};
 	uart_init();
 	console_init();
-#if 0
-	print_debug(" XIP_ROM_BASE: ");
-	print_debug_hex32(XIP_ROM_BASE);
-	print_debug(" XIP_ROM_SIZE: ");
-	print_debug_hex32(XIP_ROM_SIZE);
+	setup_default_resource_map();
+	setup_coherent_ht_domain();
+	enumerate_ht_chain(0);
+	distinguish_cpu_resets(0);
+	
+	enable_smbus();
+
+	memreset_setup();
+	sdram_initialize(1, cpu);
+
+	msr_t msr;
+	msr = rdmsr(TOP_MEM);
+	print_debug("TOP_MEM: ");
+	print_debug_hex32(msr.hi);
+	print_debug_hex32(msr.lo);
 	print_debug("\r\n");
-#endif
-	if (boot_cpu() && !cpu_init_detected()) {
-		setup_default_resource_map();
-		setup_coherent_ht_domain();
-		enumerate_ht_chain();
-		print_pci_devices();
-		enable_smbus();
-		dump_spd_registers(&cpu0);
-		sdram_initialize(&cpu0);
-
-		dump_pci_device(PCI_DEV(0, 0x18, 2));
-		
-		/* Check the first 512M */
-		msr_t msr;
-		msr = rdmsr(TOP_MEM);
-		print_debug("TOP_MEM: ");
-		print_debug_hex32(msr.hi);
-		print_debug_hex32(msr.lo);
-		print_debug("\r\n");
-		ram_check(0x00000000, msr.lo);
-	}
+
+	ram_check(0x00000000, msr.lo);
+	
 }
diff --git a/src/mainboard/amd/solo/failover.c b/src/mainboard/amd/solo/failover.c
index 017b03862f..8eeeaef7e1 100644
--- a/src/mainboard/amd/solo/failover.c
+++ b/src/mainboard/amd/solo/failover.c
@@ -2,22 +2,37 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
+#include <arch/io.h>
 #include "arch/romcc_io.h"
 #include "pc80/mc146818rtc_early.c"
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
+#include "cpu/p6/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
 
 static void main(void)
 {
 	/* Nothing special needs to be done to find bus 0 */
 	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
+	enumerate_ht_chain(0);
 
 	/* Setup the 8111 */
 	amd8111_enable_rom();
 
-	if (do_normal_boot()) {
-		/* Jump to the normal image */
+	/* Is this a cpu reset? */
+	if (cpu_init_detected()) {
+		if (last_boot_normal()) {
+			asm("jmp __normal_image");
+		} else {
+			asm("jmp __cpu_reset");
+		}
+	}
+	/* Is this a secondary cpu? */
+	else if (!boot_cpu() && last_boot_normal()) {
+		asm("jmp __normal_image");
+	}
+	/* This is the primary cpu how should I boot? */
+	else if (do_normal_boot()) {
 		asm("jmp __normal_image");
 	}
 }