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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-03-15 15:45:44 -0700
committerMartin Roth <martinroth@google.com>2018-03-19 14:19:46 +0000
commit6dfbb593077ea3edb9162431c2380a268d35fc4a (patch)
treeaf60b48533a4a0c07140d42e96d8c561c152163a /src/mainboard/amd
parent6bff3bf4be7fd94e6ffd080e498bbe75c75418d9 (diff)
downloadcoreboot-6dfbb593077ea3edb9162431c2380a268d35fc4a.tar.xz
soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uart
The GPIO programming of configure_stoneyridge_UART() can be done by the early GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart() became redundant. Remove procedure configure_stoneyridge_uart(). BUG=b:74258015 TEST=Build and boot kahlee, observing serial output does not changes from previous serial output. Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25192 Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/gardenia/gpio.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c
index 2d73ee08d2..c274a76bc6 100644
--- a/src/mainboard/amd/gardenia/gpio.c
+++ b/src/mainboard/amd/gardenia/gpio.c
@@ -35,6 +35,16 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {
{GPIO_116, Function1, FCH_GPIO_PULL_DOWN_ENABLE | INPUT },
/* SD power */
{GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H },
+ /* GPIO_136 - UART0_FCH_RX_DEBUG_RX */
+ {GPIO_136, Function0, INPUT },
+ /* GPIO_137 - UART0_FCH_DEBUG_RTS */
+ {GPIO_137, Function0, INPUT },
+ /* GPIO_138 - UART0_FCH_TX_DEBUG_RX */
+ {GPIO_138, Function0, INPUT },
+ /* GPIO_142 - UART1_FCH_RTS */
+ {GPIO_142, Function0, INPUT },
+ /* GPIO_143 - UART1_FCH_TX */
+ {GPIO_143, Function0, INPUT },
};
const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {