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authorAaron Durbin <adurbin@chromium.org>2013-04-03 09:56:57 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-04-03 19:26:25 +0200
commitc6f27226a84434182771dbbcd593d223072801f7 (patch)
tree589bd58ab19f04ac454d299549d18e15c5d87f0e /src/mainboard/amd
parent23f50166c64be0c1d3656ca67839843bf11a5274 (diff)
downloadcoreboot-c6f27226a84434182771dbbcd593d223072801f7.tar.xz
sandybridge: enable ROM caching
If ROM caching is selected the sandybridge chipset code will will enable ROM caching after all other CPU threads are brought up. Change-Id: I3a57ba8753678146527ebf9547f5fbbd4f441f43 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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