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authorRonald G. Minnich <rminnich@gmail.com>2006-04-27 15:10:55 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-04-27 15:10:55 +0000
commit3716427e7f63fd00e8117fca2027f2fe3a5bbf00 (patch)
tree6250710970f5c19492a76378c191d2590a496fcf /src/mainboard/amd
parentb7a09b4f19aa5e9d23118d32e523470e590318eb (diff)
downloadcoreboot-3716427e7f63fd00e8117fca2027f2fe3a5bbf00.tar.xz
we don't need msr_init
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/rumba/auto.c20
1 files changed, 0 insertions, 20 deletions
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index b3a9b839ee..fbc272ffd0 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -102,22 +102,6 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
-static void msr_init(void)
-{
- /* total physical memory */
- __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
-
- /* traditional memory 0kB-512kB, 512kB-1MB */
- __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-
- __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
- __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-
- /* put code in northbridge[init].c here */
-}
-
-
static void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
@@ -125,8 +109,6 @@ static void main(unsigned long bist)
};
SystemPreInit();
-
-
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
@@ -140,8 +122,6 @@ static void main(unsigned long bist)
sdram_initialize(1, memctrl);
- msr_init();
-
/* Check all of memory */
//ram_check(0x00000000, 640*1024);
}