diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/mainboard/amd | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
| download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/bimini_fam10/romstage.c | 5 | ||||
| -rw-r--r-- | src/mainboard/amd/mahogany_fam10/romstage.c | 5 | ||||
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 5 | ||||
| -rw-r--r-- | src/mainboard/amd/tilapia_fam10/romstage.c | 5 |
4 files changed, 12 insertions, 8 deletions
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 5ee1fd6ab8..f6bb70fe2c 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -33,6 +33,7 @@ #include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> +#include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> #include <southbridge/amd/sb800/smbus.h> @@ -151,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -169,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 0e2db0402f..4a244eb376 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -37,6 +37,7 @@ #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> +#include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> @@ -156,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -174,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index ad3157fbf6..622784be51 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -35,6 +35,7 @@ #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> +#include <cpu/amd/msr.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <northbridge/amd/amdfam10/raminit.h> @@ -253,7 +254,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -271,7 +272,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 89e72eb8f7..0e60fc5c75 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -35,6 +35,7 @@ #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> +#include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> #include <southbridge/amd/sb700/sb700.h> @@ -152,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -170,7 +171,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif |