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authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2014-04-18 01:42:19 -0500
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2014-04-21 21:32:34 +0200
commit44f2fab89a099b055e3ad7dc5cfe2fbeb82467e6 (patch)
tree98a6179515c025c4e5c4423cce4d581766e16c76 /src/mainboard/amd
parentce7a8024ffa079590cbc841b7d2fd78770a59c3b (diff)
downloadcoreboot-44f2fab89a099b055e3ad7dc5cfe2fbeb82467e6.tar.xz
AMD hudson and yangtze boards: Let mainboard declare power button
The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and always had the wake source declared as GPE3. This is not the correct wake source for all boards. On some laptops declaring a wake source is not needed, as the wake mechanism is handled by the EC. Move the declaration of the power button to mainboard ASL files, and scope it as \_SB.PWRB . This also makes the naming consistent with the examples in the ACPI spec. The wake source for the PWRB of HP Pavilion M6 1035dx is removed, as it is incorrect. Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5546 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/olivehill/acpi/gpe.asl8
-rw-r--r--src/mainboard/amd/olivehill/dsdt.asl7
-rw-r--r--src/mainboard/amd/parmer/acpi/gpe.asl8
-rw-r--r--src/mainboard/amd/parmer/dsdt.asl7
-rw-r--r--src/mainboard/amd/thatcher/acpi/gpe.asl8
-rw-r--r--src/mainboard/amd/thatcher/dsdt.asl7
6 files changed, 33 insertions, 12 deletions
diff --git a/src/mainboard/amd/olivehill/acpi/gpe.asl b/src/mainboard/amd/olivehill/acpi/gpe.asl
index f29450222d..8d4f8a2159 100644
--- a/src/mainboard/amd/olivehill/acpi/gpe.asl
+++ b/src/mainboard/amd/olivehill/acpi/gpe.asl
@@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* Legacy PM event */
@@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* ExtEvent0 SCI event */
@@ -66,13 +66,13 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */
diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl
index e0c21cf09f..d2d8122631 100644
--- a/src/mainboard/amd/olivehill/dsdt.asl
+++ b/src/mainboard/amd/olivehill/dsdt.asl
@@ -56,6 +56,13 @@ DefinitionBlock (
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl"
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
Device(PCI0) {
/* Describe the AMD Northbridge */
#include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl
index 40a19d405a..22a3957cbe 100644
--- a/src/mainboard/amd/parmer/acpi/gpe.asl
+++ b/src/mainboard/amd/parmer/acpi/gpe.asl
@@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* Legacy PM event */
@@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* ExtEvent0 SCI event */
@@ -67,13 +67,13 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */
diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl
index ef2ae6f8e6..21b2090bee 100644
--- a/src/mainboard/amd/parmer/dsdt.asl
+++ b/src/mainboard/amd/parmer/dsdt.asl
@@ -55,6 +55,13 @@ DefinitionBlock (
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl"
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
Device(PCI0) {
/* Describe the AMD Northbridge */
#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl
index 40a19d405a..22a3957cbe 100644
--- a/src/mainboard/amd/thatcher/acpi/gpe.asl
+++ b/src/mainboard/amd/thatcher/acpi/gpe.asl
@@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* Legacy PM event */
@@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* ExtEvent0 SCI event */
@@ -67,13 +67,13 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */
diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl
index ef2ae6f8e6..21b2090bee 100644
--- a/src/mainboard/amd/thatcher/dsdt.asl
+++ b/src/mainboard/amd/thatcher/dsdt.asl
@@ -55,6 +55,13 @@ DefinitionBlock (
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl"
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
Device(PCI0) {
/* Describe the AMD Northbridge */
#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 21:03:20 +0000