diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-14 11:40:34 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-14 11:40:34 +0000 |
commit | 5d3dee8334c2303434d7b00bec3aad4911120ac1 (patch) | |
tree | 38fd30e2473dc76d9cd64092133127934f184e9e /src/mainboard/amd | |
parent | 4154c668f24da79672099dfac06f5263c415fee0 (diff) | |
download | coreboot-5d3dee8334c2303434d7b00bec3aad4911120ac1.tar.xz |
drop quite a lot of dead code that did nothing but produce warnings and make
the rest of the code unreadable.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r-- | src/mainboard/amd/dbm690t/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/amd/mahogany/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/amd/mahogany_fam10/romstage.c | 10 | ||||
-rw-r--r-- | src/mainboard/amd/pistachio/romstage.c | 4 | ||||
-rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 6 |
5 files changed, 5 insertions, 19 deletions
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 802f0ae08c..380811d79f 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -54,7 +54,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 513376b497..adf15ee7e0 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -54,7 +54,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8718f/it8718f_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 18649f79cd..1f5366912d 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -71,14 +71,6 @@ static int smbus_read_byte(u32 device, u32 address); #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdfam10/debug.c" -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -245,9 +237,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - post_code(0x3D); - memreset_setup(); post_code(0x40); // die("Die Before MCT init."); diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 85b833f21f..775403e4f3 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -48,7 +48,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -57,7 +57,7 @@ #include "southbridge/amd/sb600/sb600_early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ -/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ +/* CAN'T BE REMOVED! memory bus reset hook for some broken amd k8 boards. */ static void memreset(int controllers, const struct mem_controller *ctrl) { } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 5dc149e70f..316e257dc1 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -68,7 +68,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #include "northbridge/amd/amdfam10/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -81,10 +81,6 @@ static void memreset_setup(void) outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - static void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 |