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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-03-14 20:17:35 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-03-14 20:17:35 +0000 |
| commit | a83b9762fce9012161eb39813f357dee673670aa (patch) | |
| tree | 4826b03781c4a81d7936d7b1195c941074901c6a /src/mainboard/amd | |
| parent | a41ff52ba9eceb0ef72eddc8f2c14be5751d85a3 (diff) | |
| download | coreboot-a83b9762fce9012161eb39813f357dee673670aa.tar.xz | |
for different pll values.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/rumba/auto.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c index 6b2fd758c0..744cba17d8 100644 --- a/src/mainboard/amd/rumba/auto.c +++ b/src/mainboard/amd/rumba/auto.c @@ -42,7 +42,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { #define PLLMSRhi 0x00001490 #define PLLMSRlo 0x02000030 -#define PLLMSRhi2 ((0xde << 16) | (1 << 26) | (1 << 24)) +#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24)) #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0)) #include "northbridge/amd/gx2/pll_reset.c" |