Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.

Without a (currently) dummy set_debug_port() function the build fails,
this may or may not be fixed differently in the future.

Manually build-tested on all SB600/SB700 boards, and tested on hardware on
one SB600 board I own, works fine.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 58 insertions, 1 deletions

diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 5988b75cd7..0fc2e43a6d 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -52,6 +52,11 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
+#if CONFIG_USBDEBUG
+#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
+#endif
+
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
@@ -123,6 +128,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* it8712f_enable_serial does not use its 1st parameter. */
 	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
+
+#if CONFIG_USBDEBUG
+	sb600_enable_usbdebug(0);
+	early_usbdebug_init();
+#endif
+
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 1b3275599e..9626efa080 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -52,6 +52,11 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8718f/it8718f_early_serial.c"
 
+#if CONFIG_USBDEBUG
+#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
+#endif
+
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
@@ -122,6 +127,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
+
+#if CONFIG_USBDEBUG
+	sb700_enable_usbdebug(0);
+	early_usbdebug_init();
+#endif
+
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 707d7f2a7b..d7f8cb9c48 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -60,6 +60,12 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
+
+#if CONFIG_USBDEBUG
+#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
+#endif
+
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -138,6 +144,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
+
+#if CONFIG_USBDEBUG
+	sb700_enable_usbdebug(0);
+	early_usbdebug_init();
+#endif
+
 	console_init();
 	printk(BIOS_DEBUG, "\n");
 
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 182fab8a0b..a3909f4799 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -46,6 +46,11 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
+#if CONFIG_USBDEBUG
+#include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
+#endif
+
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
@@ -117,8 +122,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sb600_lpc_init();
 
 	/* Pistachio used a FPGA to enable serial debug instead of a SIO
-	 * and it doens't require any special setup. */
+	 * and it doesn't require any special setup. */
 	uart_init();
+
+#if CONFIG_USBDEBUG
+	sb600_enable_usbdebug(0);
+	early_usbdebug_init();
+#endif
+
 	console_init();
 
 	post_code(0x03);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 70ba6a7e00..2971a7fc8a 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -60,6 +60,12 @@
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
+
+#if CONFIG_USBDEBUG
+#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
+#include "pc80/usbdebug_serial.c"
+#endif
+
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -138,6 +144,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
+
+#if CONFIG_USBDEBUG
+	sb700_enable_usbdebug(0);
+	early_usbdebug_init();
+#endif
+
 	console_init();
 	printk(BIOS_DEBUG, "\n");