AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()

Change-Id: I7fd14c17242cd3deb7a784fc918ad6fe1191bd13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6359
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

14 files changed, 84 insertions, 141 deletions

diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
index c39decfed7..fb939abfee 100644
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -31,12 +31,9 @@
  * and acpi_tables busnum is default.
  */
 u8 bus_sb800[6];
-u32 apicid_sb800;
 
 void get_bus_conf(void)
 {
-	u32 apicid_base;
-
 	device_t dev;
 	int i;
 
@@ -60,8 +57,4 @@ void get_bus_conf(void)
 		}
 	}
 
-	/* I/O APICs:   APIC ID Version State   Address */
-	apicid_base = CONFIG_MAX_CPUS;
-	apicid_sb800 = apicid_base;
-
 }
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 4a57d3c002..7686bd2ff7 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -22,13 +22,12 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam14.h>
 #include <SBPLATFORM.h>
 
-extern u32 apicid_sb800;
-
 u8 intr_data[] = {
 	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
 	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -48,6 +47,14 @@ static void *smp_write_config_table(void *v)
 	struct mp_config_table *mc;
 	int bus_isa;
 
+	/*
+	 * By the time this function gets called, the IOAPIC registers
+	 * have been written so they can be read to get the correct
+	 * APIC ID and Version
+	 */
+	u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);
@@ -58,14 +65,10 @@ static void *smp_write_config_table(void *v)
 	mptable_write_buses(mc, NULL, &bus_isa);
 
 	/* I/O APICs:   APIC ID Version State   Address */
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
 
-	u32 dword;
 	u8 byte;
 
-	ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
-	dword &= 0xFFFFFFF0;
-	smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
 	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
 		outb(byte | 0x80, 0xC00);
 		outb(intr_data[byte], 0xC01);
@@ -75,13 +78,13 @@ static void *smp_write_config_table(void *v)
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
 	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
 
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, fn, pin) \
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
 
 	/* APU Internal Graphic Device*/
 	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c
index 2765ed7c3f..582d7ed8c5 100644
--- a/src/mainboard/amd/olivehill/get_bus_conf.c
+++ b/src/mainboard/amd/olivehill/get_bus_conf.c
@@ -33,13 +33,10 @@
  * and acpi_tables busnum is default.
  */
 u8 bus_yangtze[6];
-u32 apicid_yangtze;
 
 
 void get_bus_conf(void)
 {
-	u32 apicid_base;
-
 	device_t dev;
 	int i;
 	memset(bus_yangtze, 0, sizeof(bus_yangtze));
@@ -59,8 +56,4 @@ void get_bus_conf(void)
 			bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		}
 	}
-
-	/* I/O APICs:   APIC ID Version State   Address */
-	apicid_base = CONFIG_MAX_CPUS;
-	apicid_yangtze = apicid_base;
 }
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index c06863b1a7..db4a3ffa8e 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -21,6 +21,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
 #include <cpu/x86/lapic.h>
 #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
 
-#define IO_APIC_ID    CONFIG_MAX_CPUS
-extern u32 apicid_yangtze;
-
 u8 picr_data[0x54] = {
 	0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
 	0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
 	int bus_isa;
-	u32 dword;
 	u8 byte;
 
+	/*
+	 * By the time this function gets called, the IOAPIC registers
+	 * have been written so they can be read to get the correct
+	 * APIC ID and Version
+	 */
+	u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,19 +92,9 @@ static void *smp_write_config_table(void *v)
 	my_smp_write_bus(mc, bus_isa, "ISA   ");
 
 	/* I/O APICs:   APIC ID Version State   Address */
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
 
-	dword = 0;
-	dword = pm_read8(0x34) & 0xF0;
-	dword |= (pm_read8(0x35) & 0xFF) << 8;
-	dword |= (pm_read8(0x36) & 0xFF) << 16;
-	dword |= (pm_read8(0x37) & 0xFF) << 24;
-	/* Set IO APIC ID onto IO_APIC_ID */
-	write32 (dword, 0x00);
-	write32 (dword + 0x10, IO_APIC_ID << 24);
-	apicid_yangtze = IO_APIC_ID;
-	smp_write_ioapic(mc, apicid_yangtze, 0x21, dword);
-
-	smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000);
+	smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
 	/* PIC IRQ routine */
 	for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
 		outb(byte, 0xC00);
@@ -153,13 +148,13 @@ static void *smp_write_config_table(void *v)
 	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin)				\
 	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
 
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin))
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
 
 	/* Internal VGA */
 	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c
index 3b3daf959f..8ff9ed35ac 100644
--- a/src/mainboard/amd/parmer/get_bus_conf.c
+++ b/src/mainboard/amd/parmer/get_bus_conf.c
@@ -33,13 +33,10 @@
  * and acpi_tables busnum is default.
  */
 u8 bus_hudson[6];
-u32 apicid_hudson;
 
 
 void get_bus_conf(void)
 {
-	u32 apicid_base;
-
 	device_t dev;
 	int i;
 
@@ -64,8 +61,4 @@ void get_bus_conf(void)
 			bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		}
 	}
-
-	/* I/O APICs:   APIC ID Version State   Address */
-	apicid_base = CONFIG_MAX_CPUS;
-	apicid_hudson = apicid_base;
 }
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 2f5179f56a..05da01a4d9 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -21,6 +21,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
 #include <cpu/x86/lapic.h>
 #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
 
-#define IO_APIC_ID    CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
-
 u8 picr_data[0x54] = {
 	0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
 	0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
 	int bus_isa;
-	u32 dword;
 	u8 byte;
 
+	/*
+	 * By the time this function gets called, the IOAPIC registers
+	 * have been written so they can be read to get the correct
+	 * APIC ID and Version
+	 */
+	u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,17 +92,7 @@ static void *smp_write_config_table(void *v)
 	my_smp_write_bus(mc, bus_isa, "ISA   ");
 
 	/* I/O APICs:   APIC ID Version State   Address */
-
-	dword = 0;
-	dword = pm_read8(0x34) & 0xF0;
-	dword |= (pm_read8(0x35) & 0xFF) << 8;
-	dword |= (pm_read8(0x36) & 0xFF) << 16;
-	dword |= (pm_read8(0x37) & 0xFF) << 24;
-	/* Set IO APIC ID onto IO_APIC_ID */
-	write32 (dword, 0x00);
-	write32 (dword + 0x10, IO_APIC_ID << 24);
-	apicid_hudson = IO_APIC_ID;
-	smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
 
 	/* PIC IRQ routine */
 	for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -114,13 +109,13 @@ static void *smp_write_config_table(void *v)
 	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin)				\
 	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
 
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
 
 	/* Internal VGA */
 	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index 9434429f5a..59881d11c2 100644
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -32,14 +32,9 @@
 * and acpi_tables busnum is default.
 */
 u8 bus_sb800[6];
-u32 apicid_sb800;
-u32 apicver_sb800;
-
 
 void get_bus_conf(void)
 {
-	u32 apicid_base;
-
 	device_t dev;
 	int i;
 
@@ -63,15 +58,5 @@ void get_bus_conf(void)
 	}
 
 
-	/* I/O APICs:    APIC ID Version State   Address */
-	apicid_base = CONFIG_MAX_CPUS;
-
-	/*
-	 * By the time this function gets called, the IOAPIC registers
-	 * have been written so they can be read to get the correct
-	 * APIC ID and Version
-	 */
-	apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
-	apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
 
 }
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 0d5f5ce931..1227d8948f 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -31,14 +31,19 @@
 #include <drivers/generic/ioapic/chip.h>
 #include <arch/ioapic.h>
 
-extern u32 apicid_sb800;
-extern u32 apicver_sb800;
-
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
 	int bus_isa;
 
+	/*
+	 * By the time this function gets called, the IOAPIC registers
+	 * have been written so they can be read to get the correct
+	 * APIC ID and Version
+	 */
+	u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
 	/* Intialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
@@ -62,20 +67,20 @@ static void *smp_write_config_table(void *v)
 	 * Type 2: I/O APICs:
 	 * APIC ID, Version, APIC Flags:EN, Address
 	 */
-	smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR);
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
 
 	/*
 	 * Type 3: I/O Interrupt Table Entries:
 	 * Int Type, Int Polarity, Int Level, Source Bus ID,
 	 * Source Bus IRQ, Dest APIC ID, Dest PIN#
 	 */
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
 
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, fn, pin) \
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
 
 	/* APU Internal Graphic Device */
 	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c
index 53c7953f3c..dcdd0b2c55 100644
--- a/src/mainboard/amd/south_station/get_bus_conf.c
+++ b/src/mainboard/amd/south_station/get_bus_conf.c
@@ -31,13 +31,10 @@
 * and acpi_tables busnum is default.
 */
 u8 bus_sb800[6];
-u32 apicid_sb800;
 
 
 void get_bus_conf(void)
 {
-  u32 apicid_base;
-
   device_t dev;
   int i;
 
@@ -63,9 +60,4 @@ void get_bus_conf(void)
     }
   }
 
-
-  /* I/O APICs:   APIC ID Version State   Address */
-  apicid_base = CONFIG_MAX_CPUS;
-  apicid_sb800 = apicid_base;
-
 }
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 57eaa0ec3a..c2ec4a26df 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -22,12 +22,12 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam14.h>
 #include <SBPLATFORM.h>
 
-extern u32 apicid_sb800;
 
 u8 intr_data[] = {
   [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -44,6 +44,14 @@ static void *smp_write_config_table(void *v)
   struct mp_config_table *mc;
   int bus_isa;
 
+	/*
+	 * By the time this function gets called, the IOAPIC registers
+	 * have been written so they can be read to get the correct
+	 * APIC ID and Version
+	 */
+	u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
   mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
   mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +62,10 @@ static void *smp_write_config_table(void *v)
   mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
 
-  u32 dword;
   u8 byte;
 
-  ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
-  dword &= 0xFFFFFFF0;
-  smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);
     outb(intr_data[byte], 0xC01);
@@ -71,13 +75,13 @@ static void *smp_write_config_table(void *v)
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
   smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 
-  mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+  mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
 
   /* PCI interrupts are level triggered, and are
    * associated with a specific bus/device/function tuple.
    */
 #define PCI_INT(bus, dev, fn, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
 
   /* APU Internal Graphic Device*/
   PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c
index 9f5f15ac87..6d0f9030c9 100644
--- a/src/mainboard/amd/thatcher/get_bus_conf.c
+++ b/src/mainboard/amd/thatcher/get_bus_conf.c
@@ -33,13 +33,10 @@
  * and acpi_tables busnum is default.
  */
 u8 bus_hudson[6];
-u32 apicid_hudson;
 
 
 void get_bus_conf(void)
 {
-	u32 apicid_base;
-
 	device_t dev;
 	int i;
 
@@ -61,8 +58,4 @@ void get_bus_conf(void)
 			bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 		}
 	}
-
-	/* I/O APICs:   APIC ID Version State   Address */
-	apicid_base = CONFIG_MAX_CPUS;
-	apicid_hudson = apicid_base;
 }
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 7f9aa7c4b2..8ddd1b6740 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -21,6 +21,7 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam15.h>
@@ -28,9 +29,6 @@
 #include <cpu/x86/lapic.h>
 #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
 
-#define IO_APIC_ID    CONFIG_MAX_CPUS
-extern u32 apicid_hudson;
-
 u8 picr_data[] = {
 	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
 	0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -70,9 +68,16 @@ static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
 	int bus_isa;
-	u32 dword;
 	u8 byte;
 
+	/*
+	 * By the time this function gets called, the IOAPIC registers
+	 * have been written so they can be read to get the correct
+	 * APIC ID and Version
+	 */
+	u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);
@@ -87,17 +92,7 @@ static void *smp_write_config_table(void *v)
 	my_smp_write_bus(mc, bus_isa, "ISA   ");
 
 	/* I/O APICs:   APIC ID Version State   Address */
-
-	dword = 0;
-	dword = pm_read8(0x34) & 0xF0;
-	dword |= (pm_read8(0x35) & 0xFF) << 8;
-	dword |= (pm_read8(0x36) & 0xFF) << 16;
-	dword |= (pm_read8(0x37) & 0xFF) << 24;
-	/* Set IO APIC ID onto IO_APIC_ID */
-	write32 (dword, 0x00);
-	write32 (dword + 0x10, IO_APIC_ID << 24);
-	apicid_hudson = IO_APIC_ID;
-	smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
 
 	/* PIC IRQ routine */
 	for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -114,13 +109,13 @@ static void *smp_write_config_table(void *v)
 	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin)				\
 	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
 
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
 
 	/* Internal VGA */
 	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c
index 52b5d884a5..8824ca1685 100644
--- a/src/mainboard/amd/union_station/get_bus_conf.c
+++ b/src/mainboard/amd/union_station/get_bus_conf.c
@@ -31,12 +31,9 @@
 * and acpi_tables busnum is default.
 */
 u8 bus_sb800[6];
-u32 apicid_sb800;
-
 
 void get_bus_conf(void)
 {
-  u32 apicid_base;
 
   device_t dev;
   int i;
@@ -66,8 +63,4 @@ void get_bus_conf(void)
   }
 
 
-  /* I/O APICs:   APIC ID Version State   Address */
-  apicid_base = CONFIG_MAX_CPUS;
-  apicid_sb800 = apicid_base;
-
 }
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 57eaa0ec3a..c2ec4a26df 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -22,12 +22,12 @@
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam14.h>
 #include <SBPLATFORM.h>
 
-extern u32 apicid_sb800;
 
 u8 intr_data[] = {
   [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
@@ -44,6 +44,14 @@ static void *smp_write_config_table(void *v)
   struct mp_config_table *mc;
   int bus_isa;
 
+	/*
+	 * By the time this function gets called, the IOAPIC registers
+	 * have been written so they can be read to get the correct
+	 * APIC ID and Version
+	 */
+	u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
   mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
   mptable_init(mc, LOCAL_APIC_ADDR);
@@ -54,14 +62,10 @@ static void *smp_write_config_table(void *v)
   mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
 
-  u32 dword;
   u8 byte;
 
-  ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
-  dword &= 0xFFFFFFF0;
-  smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
-
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);
     outb(intr_data[byte], 0xC01);
@@ -71,13 +75,13 @@ static void *smp_write_config_table(void *v)
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
   smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 
-  mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+  mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
 
   /* PCI interrupts are level triggered, and are
    * associated with a specific bus/device/function tuple.
    */
 #define PCI_INT(bus, dev, fn, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
 
   /* APU Internal Graphic Device*/
   PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);