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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-09-22 00:09:41 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-09-22 00:09:41 +0000
commit00003ae7129802d7f943756c94b35372c1b1b053 (patch)
tree1f776d8eb6b9e3a8fa28f1711e843c728a923e4d /src/mainboard/amd
parent6afb698433ba005cdfa00296fdfe07a6e11a70db (diff)
downloadcoreboot-00003ae7129802d7f943756c94b35372c1b1b053.tar.xz
If no pci access method has been set for the device tree so far (e.g.
during early coreboot_ram), pci_{read,write}_config{8,16,32} will die(). This patch changes pci_{read,write}_config{8,16,32} to use the existing PCI access method autodetection infrastructure instead of die()ing. Until r4340, any usage of pci_{read,write}_config{8,16,32} in coreboot_ram before the device tree was set up resulted in either a silent hang or a NULL pointer dereference. I changed the code in r4340 to die() properly with a loud error message. That still was not perfect, but at least it allowed people to see why their new ports died. Still, die() is not something developers like to see, and thus a patch to automatically pick a sensible default instead of dying was created. Of course, handling PCI access method selection automatically for fallback purposes has certain limitations before the device tree is set up. We only check if conf1 works and use conf2 as fallback. No further tests are done. This patch enables cleanups and readability improvements in early coreboot_ram code: Without this patch: dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64); With this patch: dword = pci_read_config32(sm_dev, 0x64); Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
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