diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-15 12:39:29 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-15 12:39:29 +0000 |
| commit | 23836e2345282151b0b46de6cdcd2bb2faee87f6 (patch) | |
| tree | e1e416ae11a78b455a26f378f33d0a8db6fa69af /src/mainboard/amd | |
| parent | c30a6e859e20dbadbad006f2f93068e7f9c36043 (diff) | |
| download | coreboot-23836e2345282151b0b46de6cdcd2bb2faee87f6.tar.xz | |
zero warnings days...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/dbm690t/mainboard.c | 7 | ||||
| -rw-r--r-- | src/mainboard/amd/mahogany/mainboard.c | 8 | ||||
| -rw-r--r-- | src/mainboard/amd/mahogany_fam10/mainboard.c | 8 | ||||
| -rw-r--r-- | src/mainboard/amd/pistachio/mainboard.c | 8 | ||||
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah/romstage.c | 5 |
5 files changed, 9 insertions, 27 deletions
diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index dfee7c0479..2f54bfdc68 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -21,12 +21,11 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <../southbridge/amd/sb600/sb600.h> +#include <southbridge/amd/sb600/sb600.h> #include "chip.h" #define ADT7461_ADDRESS 0x4C @@ -36,8 +35,6 @@ extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) #define ARA_read_byte(address) \ diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 44752f1e91..0aea2c65ea 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -21,19 +21,15 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <arch/coreboot_tables.h> -#include <../southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/sb700.h> #include "chip.h" #define SMBUS_IO_BASE 0x6000 -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); - uint64_t uma_memory_base, uma_memory_size; void set_pcie_dereset(void); diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 82a9b9eeef..c877914f86 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -21,19 +21,15 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <arch/coreboot_tables.h> -#include <../southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/sb700.h> #include "chip.h" #define SMBUS_IO_BASE 0x6000 -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); - uint64_t uma_memory_base, uma_memory_size; void set_pcie_dereset(void); diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index be36458204..d1d9a849fc 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -21,12 +21,11 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <../southbridge/amd/sb600/sb600.h> +#include <southbridge/amd/sb600/sb600.h> #include "chip.h" #define ADT7475_ADDRESS 0x2E @@ -35,9 +34,6 @@ extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); - #define ADT7475_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address) #define ADT7475_write_byte(address, val) \ diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 9b482e4578..00d4b3b21a 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -101,12 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "northbridge/amd/amdk8/amdk8.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" /* tyan does not want the default */ |