diff options
| author | Zheng Bao <fishbaozi@gmail.com> | 2015-11-09 20:22:36 +0800 |
|---|---|---|
| committer | Zheng Bao <zheng.bao@amd.com> | 2015-11-12 09:26:08 +0100 |
| commit | 861f920cdfa1f8a322ecd2a56da8c8a9fdfd1155 (patch) | |
| tree | c0b5590d370c1ee2ff4003798e20e72b00647beb /src/mainboard/amd | |
| parent | 266609968b94c9b739dedcb6861ea1b50f34be85 (diff) | |
| download | coreboot-861f920cdfa1f8a322ecd2a56da8c8a9fdfd1155.tar.xz | |
AMD/Mullins: Fix the interrupt routing
The plugged devices on PCIe should use IOAPIC2 instead of standard
IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1.
The unchanged code worked because the OS uses MSI instead APIC.
To test that, boot linux with parameter pci=nomsi and see if the devices
like NIC work well as they do without the booting parameter.
run 'cat /proc/interrupts' to see if devices actually use
no-msi.
Change-Id: I5eab28956b7a3fbc7c10447e99d6c11dbe6a1d14
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12363
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/olivehillplus/acpi/routing.asl | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/src/mainboard/amd/olivehillplus/acpi/routing.asl b/src/mainboard/amd/olivehillplus/acpi/routing.asl index ddf6404916..7cb7a2f44c 100644 --- a/src/mainboard/amd/olivehillplus/acpi/routing.asl +++ b/src/mainboard/amd/olivehillplus/acpi/routing.asl @@ -75,10 +75,10 @@ Name(APR0, Package(){ Package(){0x0001FFFF, 1, 0, 45 }, /* Bus 0, Dev 2 - PCIe Bridges */ - Package(){0x0002FFFF, 0, 0, 18 }, - Package(){0x0002FFFF, 1, 0, 19 }, - Package(){0x0002FFFF, 2, 0, 16 }, - Package(){0x0002FFFF, 3, 0, 17 }, + Package(){0x0002FFFF, 0, 0, 24 }, + Package(){0x0002FFFF, 1, 0, 25 }, + Package(){0x0002FFFF, 2, 0, 26 }, + Package(){0x0002FFFF, 3, 0, 27 }, /* SB devices in APIC mode */ @@ -130,10 +130,10 @@ Name(PS4, Package(){ }) Name(APS4, Package(){ /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, }) /* GPP 0 */ @@ -144,10 +144,10 @@ Name(PS5, Package(){ Package(){0x0000FFFF, 3, INTA, 0 }, }) Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, }) /* GPP 1 */ @@ -158,10 +158,10 @@ Name(PS6, Package(){ Package(){0x0000FFFF, 3, INTB, 0 }, }) Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, }) /* GPP 2 */ @@ -172,10 +172,10 @@ Name(PS7, Package(){ Package(){0x0000FFFF, 3, INTC, 0 }, }) Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, }) /* GPP 3 */ @@ -186,8 +186,8 @@ Name(PS8, Package(){ Package(){0x0000FFFF, 3, INTD, 0 }, }) Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 18 }, + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, }) |