diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-23 19:54:12 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-24 16:12:44 +0000 |
| commit | 9796f60c62f57ac512f225809c10b5b09ef80f5a (patch) | |
| tree | 5d6c3e1d933782bbb03af4ac7a21579f722b5327 /src/mainboard/amd | |
| parent | a40032780fe4da7d95b203fb3d05a25183590952 (diff) | |
| download | coreboot-9796f60c62f57ac512f225809c10b5b09ef80f5a.tar.xz | |
coreboot: move TS_END_ROMSTAGE to one spot
While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
timestamp table.
Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/bimini_fam10/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/mahogany_fam10/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/tilapia_fam10/romstage.c | 2 |
4 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 372074c5ae..9e2e9044b0 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -225,8 +225,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_before_pci_init(); sb800_before_pci_init(); - timestamp_add_now(TS_END_ROMSTAGE); - post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 2836d672e3..c01ccf0a37 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); - timestamp_add_now(TS_END_ROMSTAGE); - post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 631534ec29..3d7c168479 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -333,8 +333,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("After MCT init before CAR disabled."); - timestamp_add_now(TS_END_ROMSTAGE); - post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 12c92441ae..924345d51a 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); - timestamp_add_now(TS_END_ROMSTAGE); - post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. |