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| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-05-14 11:02:56 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-05-14 11:02:56 +0000 |
| commit | c928a295b3c23cc0fad0e40d9ddd9ffff3b0660a (patch) | |
| tree | 2eb99895ff21ba9875455bcb6b5052a6f1802aff /src/mainboard/amd | |
| parent | 930d32ba8741f059280feba79006da710411faeb (diff) | |
| download | coreboot-c928a295b3c23cc0fad0e40d9ddd9ffff3b0660a.tar.xz | |
Remove another set of includes from Fam10 romstages:
northbridge/amd/amdht/ht_wrapper.c
northbridge/amd/amdfam10/raminit_amdmct.c
cpu/amd/model_10xxx/fidvid.c
pc80/mc146818rtc_early.c
They are now included by the fam10 chipset code that requires them.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/mahogany_fam10/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/amd/tilapia_fam10/romstage.c | 4 |
3 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index de8058e308..fa08e357b3 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -46,7 +46,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include <console/console.h> #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> @@ -82,10 +81,8 @@ static int spd_read_byte(u32 device, u32 address) } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -95,7 +92,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 17cee75840..038fbedff9 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -46,7 +46,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include <console/console.h> #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> @@ -104,10 +103,8 @@ static int spd_read_byte(u32 device, u32 address) } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -117,7 +114,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index d0bbaa4026..d8458d7fb1 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -46,7 +46,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" -#include "pc80/mc146818rtc_early.c" #include <console/console.h> #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> @@ -82,10 +81,8 @@ static int spd_read_byte(u32 device, u32 address) } #include "northbridge/amd/amdfam10/amdfam10.h" -#include "northbridge/amd/amdht/ht_wrapper.c" #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "resourcemap.c" @@ -95,7 +92,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "cpu/amd/model_10xxx/fidvid.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" |