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authorFelix Held <felix.held@amd.corp-partner.google.com>2020-06-13 02:10:09 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-06-21 01:56:22 +0000
commitfe1d80cb08213a302a80714114ea3b9e632411ff (patch)
tree8f73a5980a6edfda931d44445b6b848da8f4932f /src/mainboard/amd
parente6315f74d6f402734e476a57a8faf4ac9cb23d38 (diff)
downloadcoreboot-fe1d80cb08213a302a80714114ea3b9e632411ff.tar.xz
amd/mandolin: unbreak SeaBIOS VBIOS support
Commit 86ba0d73f34185533e5e2d4258aa3bf3dba40ed4 added VBIOS support for Raven2 silicon and changed the VBIOS file names to the format including the PCI device revision number. Upstream SeaBIOS expects the file to have only the PCI vendor and device IDs in the CBFS file name, so it doesn't find the VBIOS any more after that patch got applied. This patch adds the path and CBFS file name to include the Picasso VBIOS a second time under the CBFS file name SeaBIOS expects. This is a workaround and not a clean solution, but avoids breakage. It's separated from the rest of the Mandolin support, so it can just be reverted after a proper fix is implemented. https://chromium-review.googlesource.com/2015963/ in combination with a links file in CBFS might solve the issue for most of the cases, but it's not sure yet if for all, so a proper fix might require more than that. BUG=b:153675508 Change-Id: I4d9042615965b6a2d9255c194cf23368264ffe54 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42433 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/mandolin/Kconfig12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig
index 9760e45194..6ec77bf01d 100644
--- a/src/mainboard/amd/mandolin/Kconfig
+++ b/src/mainboard/amd/mandolin/Kconfig
@@ -91,4 +91,16 @@ config PICASSO_LPC_IOMUX
Picasso's LPC bus signals are MUXed with some of the EMMC signals.
Select this option if LPC signals are required.
+#TODO: remove this hack to not break graphics in combination with SeaBIOS
+config VGA_BIOS_DGPU_ID
+ string
+ default "1002,15d8"
+ help
+ The default VGA BIOS PCI vendor/device ID should be set to the
+ result of the map_oprom_vendev() function in northbridge.c.
+
+config VGA_BIOS_DGPU_FILE
+ string
+ default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin"
+
endif # BOARD_AMD_MANDOLIN