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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-10-21 14:19:04 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-03 08:11:03 +0100
commit1aa35c6f6c2f3d3820d574579e929cbafd4304a7 (patch)
treee7f6a20ca94317095c8eea789ff8d380f5be5a11 /src/mainboard/amd
parentb139b5efcc7f1caf541156fa8d213e3eaf231603 (diff)
downloadcoreboot-1aa35c6f6c2f3d3820d574579e929cbafd4304a7.tar.xz
AGESA: Trace execution with AGESA_EVENTLOG()
Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7604 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/dinar/romstage.c11
-rw-r--r--src/mainboard/amd/inagua/romstage.c11
-rw-r--r--src/mainboard/amd/olivehill/romstage.c15
-rw-r--r--src/mainboard/amd/parmer/romstage.c15
-rw-r--r--src/mainboard/amd/persimmon/romstage.c15
-rw-r--r--src/mainboard/amd/south_station/romstage.c11
-rw-r--r--src/mainboard/amd/thatcher/romstage.c15
-rw-r--r--src/mainboard/amd/torpedo/romstage.c11
-rw-r--r--src/mainboard/amd/union_station/romstage.c11
9 files changed, 53 insertions, 62 deletions
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 3b13ee62ed..b1e9a61ec2 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -30,7 +30,6 @@
#include <console/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h"
#include <superio/smsc/sch4037/sch4037.h>
#include <superio/smsc/sio1036/sio1036.h>
@@ -64,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
post_code(0x32);
- AGESAWRAPPER(amdinitmmio);
+ agesawrapper_amdinitmmio();
/* Halt if there was a built in self test failure */
post_code(0x33);
@@ -81,10 +80,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
post_code(0x35);
- AGESAWRAPPER(amdinitreset);
+ agesawrapper_amdinitreset();
post_code(0x36);
- AGESAWRAPPER(amdinitearly);
+ agesawrapper_amdinitearly();
post_code(0x37);
nb_Poweron_Init();
@@ -93,10 +92,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
- AGESAWRAPPER(amdinitpost);
+ agesawrapper_amdinitpost();
post_code(0x40);
- AGESAWRAPPER(amdinitenv);
+ agesawrapper_amdinitenv();
post_code(0x43);
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index e0cf1d3b05..3a5c761530 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -32,7 +32,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h"
#include <superio/smsc/kbc1100/kbc1100.h>
#include "cpu/x86/lapic.h"
@@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
+ agesawrapper_amdinitmmio();
post_code(0x37);
- AGESAWRAPPER(amdinitreset);
+ agesawrapper_amdinitreset();
post_code(0x39);
- AGESAWRAPPER(amdinitearly);
+ agesawrapper_amdinitearly();
post_code(0x40);
- AGESAWRAPPER(amdinitpost);
+ agesawrapper_amdinitpost();
post_code(0x41);
- AGESAWRAPPER(amdinitenv);
+ agesawrapper_amdinitenv();
post_code(0x50);
copy_and_run();
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index b1dcb5818a..abab68844a 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -31,7 +31,6 @@
#include <console/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
#include "southbridge/amd/agesa/hudson/hudson.h"
@@ -51,7 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+ agesawrapper_amdinitmmio();
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -81,29 +80,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
val = inb(0xcd6);
post_code(0x37);
- AGESAWRAPPER(amdinitreset);
+ agesawrapper_amdinitreset();
post_code(0x38);
printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
post_code(0x39);
- AGESAWRAPPER(amdinitearly);
+ agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) {
post_code(0x40);
- AGESAWRAPPER(amdinitpost);
+ agesawrapper_amdinitpost();
post_code(0x41);
- AGESAWRAPPER(amdinitenv);
+ agesawrapper_amdinitenv();
/* TODO: Disable cache is not ok. */
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
- AGESAWRAPPER(amdinitresume);
+ agesawrapper_amdinitresume();
agesawrapper_amdinitcpuio();
- AGESAWRAPPER(amds3laterestore);
+ agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index fe84a90413..9a55e8060b 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -31,7 +31,6 @@
#include <console/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
#include "southbridge/amd/agesa/hudson/hudson.h"
@@ -43,7 +42,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+ agesawrapper_amdinitmmio();
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -68,25 +67,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
- AGESAWRAPPER(amdinitreset);
+ agesawrapper_amdinitreset();
post_code(0x39);
- AGESAWRAPPER(amdinitearly);
+ agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) {
post_code(0x40);
- AGESAWRAPPER(amdinitpost);
+ agesawrapper_amdinitpost();
post_code(0x41);
- AGESAWRAPPER(amdinitenv);
+ agesawrapper_amdinitenv();
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
- AGESAWRAPPER(amdinitresume);
+ agesawrapper_amdinitresume();
agesawrapper_amdinitcpuio();
- AGESAWRAPPER(amds3laterestore);
+ agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index fbe60fc911..5434ed3fe2 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -32,7 +32,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h"
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81865f/f81865f.h>
@@ -80,29 +79,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
+ agesawrapper_amdinitmmio();
post_code(0x37);
- AGESAWRAPPER(amdinitreset);
+ agesawrapper_amdinitreset();
post_code(0x39);
- AGESAWRAPPER(amdinitearly);
+ agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) {
post_code(0x40);
- AGESAWRAPPER(amdinitpost);
+ agesawrapper_amdinitpost();
post_code(0x42);
- AGESAWRAPPER(amdinitenv);
+ agesawrapper_amdinitenv();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
- AGESAWRAPPER(amdinitresume);
+ agesawrapper_amdinitresume();
- AGESAWRAPPER(amds3laterestore);
+ agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index a64ba603e2..7dcd9b206c 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -32,7 +32,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h"
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f81865f/f81865f.h>
@@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
+ agesawrapper_amdinitmmio();
post_code(0x37);
- AGESAWRAPPER(amdinitreset);
+ agesawrapper_amdinitreset();
post_code(0x39);
- AGESAWRAPPER(amdinitearly);
+ agesawrapper_amdinitearly();
post_code(0x40);
- AGESAWRAPPER(amdinitpost);
+ agesawrapper_amdinitpost();
post_code(0x41);
- AGESAWRAPPER(amdinitenv);
+ agesawrapper_amdinitenv();
post_code(0x50);
copy_and_run();
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6a300d610d..193454542c 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -31,7 +31,6 @@
#include <console/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
#include "southbridge/amd/agesa/hudson/hudson.h"
@@ -48,7 +47,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u8 byte;
pci_devfn_t dev;
- AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+ agesawrapper_amdinitmmio();
/* Set LPC decode enables. */
dev = PCI_DEV(0, 0x14, 3);
@@ -82,25 +81,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
- AGESAWRAPPER(amdinitreset);
+ agesawrapper_amdinitreset();
post_code(0x39);
- AGESAWRAPPER(amdinitearly);
+ agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
if (!s3resume) {
post_code(0x40);
- AGESAWRAPPER(amdinitpost);
+ agesawrapper_amdinitpost();
post_code(0x41);
- AGESAWRAPPER(amdinitenv);
+ agesawrapper_amdinitenv();
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
- AGESAWRAPPER(amdinitresume);
+ agesawrapper_amdinitresume();
agesawrapper_amdinitcpuio();
- AGESAWRAPPER(amds3laterestore);
+ agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 682a76ea2c..f2bcccc519 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -29,7 +29,6 @@
#include <console/loglevel.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h"
#include <superio/smsc/kbc1100/kbc1100.h>
#include "cpu/x86/lapic.h"
@@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
post_code(0x35);
- AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+ agesawrapper_amdinitmmio();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
@@ -72,13 +71,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x36);
- AGESAWRAPPER(amdinitreset);
+ agesawrapper_amdinitreset();
post_code(0x37);
- AGESAWRAPPER(amdinitearly);
+ agesawrapper_amdinitearly();
post_code(0x38);
- AGESAWRAPPER(amdinitpost);
+ agesawrapper_amdinitpost();
post_code(0x39);
printk(BIOS_DEBUG, "sb_before_pci_init ");
@@ -86,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "passed.\n");
post_code(0x40);
- AGESAWRAPPER(amdinitenv);
+ agesawrapper_amdinitenv();
post_code(0x43);
copy_and_run();
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 7745338251..ac583dd33d 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -32,7 +32,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/lapic.h"
#include <sb_cimx.h>
@@ -69,19 +68,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x35);
- AGESAWRAPPER(amdinitmmio);
+ agesawrapper_amdinitmmio();
post_code(0x37);
- AGESAWRAPPER(amdinitreset);
+ agesawrapper_amdinitreset();
post_code(0x39);
- AGESAWRAPPER(amdinitearly);
+ agesawrapper_amdinitearly();
post_code(0x40);
- AGESAWRAPPER(amdinitpost);
+ agesawrapper_amdinitpost();
post_code(0x41);
- AGESAWRAPPER(amdinitenv);
+ agesawrapper_amdinitenv();
post_code(0x50);
copy_and_run();