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authorGaggery Tsai <gaggery.tsai@intel.com>2018-01-22 11:17:28 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2018-01-24 00:44:30 +0000
commit63278ab07d684f90804065a6351e0d138f09b507 (patch)
tree7d8aa7dd74bdacaf5770b7e1972d52b331307095 /src/mainboard/amd
parent94ef4a8a476a66931eb2b2f7f8573fed52956d0f (diff)
downloadcoreboot-63278ab07d684f90804065a6351e0d138f09b507.tar.xz
mb/google/fizz: Add AC/DC loadline settings
This patch adds AC and DC loadline settings since vr_config_enable is set. Without correct AD/DC loadline settings, VRs reported incorrect VID values which caused CPU freqency clipping. The clipping reason could be retrieved from MSR 0x64F. From VRTT report, the AC/DC loadline resistances are within spec, we can use default value defined in Table 6-1, doc #543977. BUG=b:70646304 BRANCH=None TEST=emerge-fizz coreboot chromeos-bootimage & Read AC/DC loadline settings from DCI to ensure the values were programmed correctly. Change-Id: Id0ce29fa5726ca3711aa4c822fb123e2de7bc48f Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23349 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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