Drop duplicate files that prevent building without ramstage.a

When dropping ramstage.a duplicate symbols in ramstage
will start breaking the build. Hence drop all the duplicate
functions implemented by mainboards that have those functions
in generic or component code already.

Change-Id: I5cf8245c67b6f0f348388db54256d28f47017a61
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1865
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)

10 files changed, 0 insertions, 562 deletions

diff --git a/src/mainboard/amd/bimini_fam10/reset.c b/src/mainboard/amd/bimini_fam10/reset.c
deleted file mode 100644
index 0b32bedb36..0000000000
--- a/src/mainboard/amd/bimini_fam10/reset.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <reset.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-
-#define HT_INIT_CONTROL		0x6C
-#define HTIC_BIOSR_Detect	(1<<5)
-
-#if CONFIG_MAX_PHYSICAL_CPUS > 32
-#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
-#else
-#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
-#endif
-
-static inline void set_bios_reset(void)
-{
-	u32 nodes, htic;
-	device_t dev;
-	int i;
-
-	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
-	for (i = 0; i < nodes; i++) {
-		dev = NODE_PCI(i, 0);
-		htic = pci_read_config32(dev, HT_INIT_CONTROL);
-		htic &= ~HTIC_BIOSR_Detect;
-		pci_write_config32(dev, HT_INIT_CONTROL, htic);
-	}
-}
-
-void hard_reset(void)
-{
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
-	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
-	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
-
-//SbReset();
-void soft_reset(void)
-{
-	set_bios_reset();
-	/* link reset */
-	outb(0x06, 0x0cf9);
-}
diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc
index e3452430a3..de3163d98a 100644
--- a/src/mainboard/amd/parmer/Makefile.inc
+++ b/src/mainboard/amd/parmer/Makefile.inc
@@ -28,6 +28,3 @@ ramstage-y += agesawrapper.c
 ramstage-y += dimmSpd.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += PlatformGnbPcie.c
-
-ramstage-y += reset.c
-ramstage-y += pmio.c
diff --git a/src/mainboard/amd/parmer/pmio.c b/src/mainboard/amd/parmer/pmio.c
deleted file mode 100644
index a8f1d3d4ae..0000000000
--- a/src/mainboard/amd/parmer/pmio.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <arch/io.h>	/*inb, outb*/
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
-	outb(reg, port_base);
-	outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
-	outb(reg, port_base);
-	return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
-	return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
-	return pmio_read_index(PM2_INDEX, reg);
-}
diff --git a/src/mainboard/amd/parmer/reset.c b/src/mainboard/amd/parmer/reset.c
deleted file mode 100644
index 5735fa2446..0000000000
--- a/src/mainboard/amd/parmer/reset.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <reset.h>
-#include <arch/io.h>		/*inb, outb*/
-#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
-
-#define HT_INIT_CONTROL		0x6C
-#define HTIC_BIOSR_Detect	(1<<5)
-
-#if CONFIG_MAX_PHYSICAL_CPUS > 32
-#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
-#else
-#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
-#endif
-
-static inline void set_bios_reset(void)
-{
-	u32 nodes;
-	u32 htic;
-	device_t dev;
-	int i;
-
-	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
-	for(i = 0; i < nodes; i++) {
-		dev = NODE_PCI(i, 0);
-		htic = pci_read_config32(dev, HT_INIT_CONTROL);
-		htic &= ~HTIC_BIOSR_Detect;
-		pci_write_config32(dev, HT_INIT_CONTROL, htic);
-	}
-}
-
-void hard_reset(void)
-{
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
-	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
-	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
-
-//SbReset();
-void soft_reset(void)
-{
-	set_bios_reset();
-	/* link reset */
-	outb(0x06, 0x0cf9);
-}
diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc
index e3452430a3..de3163d98a 100644
--- a/src/mainboard/amd/thatcher/Makefile.inc
+++ b/src/mainboard/amd/thatcher/Makefile.inc
@@ -28,6 +28,3 @@ ramstage-y += agesawrapper.c
 ramstage-y += dimmSpd.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += PlatformGnbPcie.c
-
-ramstage-y += reset.c
-ramstage-y += pmio.c
diff --git a/src/mainboard/amd/thatcher/fadt.c b/src/mainboard/amd/thatcher/fadt.c
deleted file mode 100644
index b72208c432..0000000000
--- a/src/mainboard/amd/thatcher/fadt.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include "pmio.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of sb800. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK		(pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK	(pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK	(pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK		(pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK		(pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL	(pm_base + 0x08) /* 6 bytes */
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-
-	pm_base &= 0xFFFF;
-	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
-	/* Prepare the header */
-	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = 244;
-	header->revision = 3;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, "COREBOOT", 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 0;
-
-	fadt->firmware_ctrl = (u32) facs;
-	fadt->dsdt = (u32) dsdt;
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
-	fadt->preferred_pm_profile = 0x03;
-	fadt->sci_int = 9;
-	/* disable system management mode by setting to 0: */
-	fadt->smi_cmd = 0;
-	fadt->acpi_enable = 0xf0;
-	fadt->acpi_disable = 0xf1;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0xe2;
-
-	#if 1
-	pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
-	pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
-	pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
-	pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
-	pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
-	pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
-	pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
-	pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
-
-	/* CpuControl is in \_PR.CPU0, 6 bytes */
-	pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
-	pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
-
-	pm_iowrite(0x6A, 0);	/* AcpiSmiCmdLo */
-	pm_iowrite(0x6B, 0);	/* AcpiSmiCmdHi */
-
-	pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
-	pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
-	#endif
-
-	pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
-					* the contents of the PM registers at
-					* index 60-6B to decode ACPI I/O address.
-					* AcpiSmiEn & SmiCmdEn*/
-	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
-	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
-	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
-	fadt->pm1b_evt_blk = 0x0000;
-	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
-	fadt->pm1b_cnt_blk = 0x0000;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;//0xFE00;//
-	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
-	fadt->gpe0_blk = ACPI_GPE0_BLK;
-	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
-
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 8;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-
-	fadt->cst_cnt = 0xe3;
-	fadt->p_lvl2_lat = 101;
-	fadt->p_lvl3_lat = 1001;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 3;
-	fadt->day_alrm = 0;	/* 0x7d these have to be */
-	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->century = 0;	/* 0x7f to make rtc alrm work */
-	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
-	fadt->flags = 0x0001c1a5 | 1 << 10;/* 0x25; */
-
-	fadt->res2 = 0;
-
-	fadt->reset_reg.space_id = 1;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0x0;
-
-	fadt->reset_value = 6;
-	fadt->x_firmware_ctl_l = (u32) facs;
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (u32) dsdt;
-	fadt->x_dsdt_h = 0;
-
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 4;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 2;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 0;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;//0xFE00;//ACPI_PMA_CNT_BLK;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 32;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-
-}
diff --git a/src/mainboard/amd/thatcher/pmio.c b/src/mainboard/amd/thatcher/pmio.c
deleted file mode 100644
index a8f1d3d4ae..0000000000
--- a/src/mainboard/amd/thatcher/pmio.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <arch/io.h>	/*inb, outb*/
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
-	outb(reg, port_base);
-	outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
-	outb(reg, port_base);
-	return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
-	return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
-	return pmio_read_index(PM2_INDEX, reg);
-}
diff --git a/src/mainboard/amd/thatcher/reset.c b/src/mainboard/amd/thatcher/reset.c
deleted file mode 100644
index 5735fa2446..0000000000
--- a/src/mainboard/amd/thatcher/reset.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <reset.h>
-#include <arch/io.h>		/*inb, outb*/
-#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
-
-#define HT_INIT_CONTROL		0x6C
-#define HTIC_BIOSR_Detect	(1<<5)
-
-#if CONFIG_MAX_PHYSICAL_CPUS > 32
-#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
-#else
-#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
-#endif
-
-static inline void set_bios_reset(void)
-{
-	u32 nodes;
-	u32 htic;
-	device_t dev;
-	int i;
-
-	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
-	for(i = 0; i < nodes; i++) {
-		dev = NODE_PCI(i, 0);
-		htic = pci_read_config32(dev, HT_INIT_CONTROL);
-		htic &= ~HTIC_BIOSR_Detect;
-		pci_write_config32(dev, HT_INIT_CONTROL, htic);
-	}
-}
-
-void hard_reset(void)
-{
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
-	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
-	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
-
-//SbReset();
-void soft_reset(void)
-{
-	set_bios_reset();
-	/* link reset */
-	outb(0x06, 0x0cf9);
-}
diff --git a/src/mainboard/amd/torpedo/Makefile.inc b/src/mainboard/amd/torpedo/Makefile.inc
index ee44adec10..96891f214b 100644
--- a/src/mainboard/amd/torpedo/Makefile.inc
+++ b/src/mainboard/amd/torpedo/Makefile.inc
@@ -45,5 +45,3 @@ ramstage-y += BiosCallOuts.c
 ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
-ramstage-y += pmio.c
-
diff --git a/src/mainboard/amd/torpedo/pmio.c b/src/mainboard/amd/torpedo/pmio.c
deleted file mode 100644
index baded54ba6..0000000000
--- a/src/mainboard/amd/torpedo/pmio.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-
-#include <arch/io.h>	/*inb, outb*/
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
-	outb(reg, port_base);
-	outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
-	outb(reg, port_base);
-	return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
-	return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
-	return pmio_read_index(PM2_INDEX, reg);
-}
-