summaryrefslogtreecommitdiff
path: root/src/mainboard/amd
diff options
context:
space:
mode:
authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-10-16 14:24:06 -0500
committerMartin Roth <martinroth@google.com>2015-11-02 23:37:24 +0100
commitb30d7ed8f09d4d5d75bf68f3ba74674fe65c4b4f (patch)
treeddc91437a60efdc74d2502fc1e321e455e5afda7 /src/mainboard/amd
parent69b11f9d407057f0ea76784ecb0e9970cb7d0991 (diff)
downloadcoreboot-b30d7ed8f09d4d5d75bf68f3ba74674fe65c4b4f.tar.xz
cpu/amd: Move model_10xxx to family_10h-family_15h
Change-Id: I34501d3fc68b71db7781dad11d5b883868932a60 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11965 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/bimini_fam10/romstage.c2
-rw-r--r--src/mainboard/amd/mahogany_fam10/romstage.c2
-rw-r--r--src/mainboard/amd/serengeti_cheetah_fam10/romstage.c2
-rw-r--r--src/mainboard/amd/tilapia_fam10/romstage.c2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index c39e7aa763..3649e84f91 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -61,7 +61,7 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
-#include "cpu/amd/model_10xxx/init_cpus.c"
+#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 2e937b6f1e..e9f240c2e4 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -64,7 +64,7 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
-#include "cpu/amd/model_10xxx/init_cpus.c"
+#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 87d7dbf6c0..6bd548bf49 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -83,7 +83,7 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
-#include "cpu/amd/model_10xxx/init_cpus.c"
+#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
static const u8 spd_addr[] = {
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index d9404942ca..d49ed577a9 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -63,7 +63,7 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/quadcore/quadcore.c"
#include <cpu/amd/microcode.h>
-#include "cpu/amd/model_10xxx/init_cpus.c"
+#include "cpu/amd/family_10h-family_15h/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>