src/mainboard/a-trend - emulation: Add space around operators

Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16616
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)

39 files changed, 163 insertions, 163 deletions

diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index be381a12ba..9ea7e44be2 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3A);
 
 	/* show final fid and vid */
-	msr=rdmsr(0xc0010071);
+	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 
diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
index c2f9c83afb..f46116ad89 100644
--- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
+++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
@@ -292,10 +292,10 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
 		/* Azalia Controller OEM Codec Table Pointer */
 		FchParams->Azalia.AzaliaPinCfg = TRUE;
 		FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){
-			.AzaliaSdin0 = (CONFIG_AZ_PIN>>0) & 0x03,
-			.AzaliaSdin1 = (CONFIG_AZ_PIN>>2) & 0x03,
-			.AzaliaSdin2 = (CONFIG_AZ_PIN>>4) & 0x03,
-			.AzaliaSdin3 = (CONFIG_AZ_PIN>>6) & 0x03
+			.AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03,
+			.AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03,
+			.AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03,
+			.AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03
 		};
 		FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList;
 		/* Azalia Controller Front Panel OEM Table Pointer */
diff --git a/src/mainboard/amd/dbm690t/fadt.c b/src/mainboard/amd/dbm690t/fadt.c
index f9768b20bd..b397f52aea 100644
--- a/src/mainboard/amd/dbm690t/fadt.c
+++ b/src/mainboard/amd/dbm690t/fadt.c
@@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	fadt->firmware_ctrl = (u32) facs;
 	fadt->dsdt = (u32) dsdt;
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
 	fadt->preferred_pm_profile = 0x03;
 	fadt->sci_int = 9;
 	/* disable system management mode by setting to 0: */
@@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
 	pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
 
-	pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
+	pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
 					* the contents of the PM registers at
 					* index 20-2B to decode ACPI I/O address.
 					* AcpiSmiEn & SmiCmdEn*/
-	pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
 	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
 
 	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
index 261ac9ad4b..76ee05681f 100644
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ b/src/mainboard/amd/dbm690t/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
 			dword = pci_read_config32(dev, 0xac);
 			dword &= ~(7 << 26);
 			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1<<22; PIC and APIC co exists */
+			/* dword |= 1 << 22; PIC and APIC co exists */
 			pci_write_config32(dev, 0xac, dword);
 
 			/*
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 517f75bc39..26275b6ee5 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -109,7 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	cpuid1 = cpuid(0x80000007);
 	if ((cpuid1.edx & 0x6) == 0x6) {
 		/* Read FIDVID_STATUS */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
@@ -117,7 +117,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		init_fidvid_bsp(bsp_apicid);
 
 		/* show final fid and vid */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 	} else {
 		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
diff --git a/src/mainboard/amd/dinar/fadt.c b/src/mainboard/amd/dinar/fadt.c
index 977a6ce664..1aad0b50ed 100644
--- a/src/mainboard/amd/dinar/fadt.c
+++ b/src/mainboard/amd/dinar/fadt.c
@@ -54,7 +54,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	else
 		fadt->dsdt = (uintptr_t)dsdt;
 
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
 	fadt->preferred_pm_profile = 0x03;
 	fadt->sci_int = 9;
 	/* disable system management mode by setting to 0: */
diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c
index 17097b33d1..affda6fd76 100644
--- a/src/mainboard/amd/dinar/gpio.c
+++ b/src/mainboard/amd/dinar/gpio.c
@@ -179,7 +179,7 @@ gpioEarlyInit(
 	RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1);      // GPIO
 	RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5);    // GPI
 
-	// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW)
+	// set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW)
 	RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
 	RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
 	RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
@@ -357,7 +357,7 @@ gpioEarlyInit(
 	}
 	//		else
 	//		{ // 0 - AUTO
-	//			// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable)
+	//			// set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable)
 	//			RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
 	//			RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
 	//		}
@@ -377,7 +377,7 @@ gpioEarlyInit(
 	}
 	//		else
 	//		{ // 0 - AUTO
-	//			// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)
+	//			// set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH)
 	//			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
 	//			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
 	//
diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h
index c61f4452f3..3ac8bfa818 100644
--- a/src/mainboard/amd/dinar/gpio.h
+++ b/src/mainboard/amd/dinar/gpio.h
@@ -341,8 +341,8 @@
 #define GPIO_228_SELECT     FUNCTION0+NonGpio   // SMBUS, DATA
 #define GPIO_229_SELECT     FUNCTION0+NonGpio   // DP1_HPD
 
-#define TYPE_GPI  (1<<5)
-#define TYPE_GPO  (0<<5)
+#define TYPE_GPI  (1 << 5)
+#define TYPE_GPO  (0 << 5)
 
 #define GPIO_00_TYPE        TYPE_GPO
 #define GPIO_01_TYPE        TYPE_GPO
@@ -578,8 +578,8 @@
 #define GPIO_228_TYPE       TYPE_GPO
 #define GPIO_229_TYPE       TYPE_GPO
 
-#define GPO_LOW   (0<<6)
-#define GPO_HI    (1<<6)
+#define GPO_LOW   (0 << 6)
+#define GPO_HI    (1 << 6)
 
 #define GPO_00_LEVEL        GPO_HI
 #define GPO_01_LEVEL        GPO_HI
@@ -812,8 +812,8 @@
 #define GPO_228_LEVEL       GPO_LOW
 #define GPO_229_LEVEL       GPO_LOW
 
-#define GPIO_NONSTICKY   (0<<2)
-#define GPIO_STICKY      (1<<2)
+#define GPIO_NONSTICKY   (0 << 2)
+#define GPIO_STICKY      (1 << 2)
 
 #define GPIO_00_STICKY      GPIO_NONSTICKY
 #define GPIO_01_STICKY      GPIO_NONSTICKY
@@ -1046,8 +1046,8 @@
 #define GPIO_228_STICKY     GPIO_NONSTICKY
 #define GPIO_229_STICKY     GPIO_NONSTICKY
 
-#define PULLUP_ENABLE      (0<<3)
-#define PULLUP_DISABLE     (1<<3)
+#define PULLUP_ENABLE      (0 << 3)
+#define PULLUP_DISABLE     (1 << 3)
 
 #define GPIO_00_PULLUP      PULLUP_DISABLE
 #define GPIO_01_PULLUP      PULLUP_DISABLE
@@ -1282,8 +1282,8 @@
 #define GPIO_228_PULLUP     PULLUP_DISABLE
 #define GPIO_229_PULLUP     PULLUP_DISABLE
 
-#define PULLDOWN_ENABLE       (1<<4)
-#define PULLDOWN_DISABLE      (0<<4)
+#define PULLDOWN_ENABLE       (1 << 4)
+#define PULLDOWN_DISABLE      (0 << 4)
 
 #define GPIO_00_PULLDOWN    PULLDOWN_DISABLE
 #define GPIO_01_PULLDOWN    PULLDOWN_DISABLE
@@ -1750,7 +1750,7 @@
 
 typedef enum _GPIO_COUNT
 {
-	GPIO_00=0,
+	GPIO_00 = 0,
 	GPIO_01,
 	GPIO_02,
 	GPIO_03,
@@ -2227,7 +2227,7 @@ GPIO_SETTINGS gpio_table[]=
 
 typedef enum _GEVENT_COUNT
 {
-	GEVENT_00=0x60,
+	GEVENT_00 = 0x60,
 	GEVENT_01,
 	GEVENT_02,
 	GEVENT_03,
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index 3a45761042..4b6405594e 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -57,7 +57,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
 	/* Get SB MMIO Base (AcpiMmioAddr) */
 	WriteIo8 (0xCD6, 0x27);
 	Data8   = ReadIo8(0xCD7);
-	Data16  = Data8<<8;
+	Data16  = Data8 << 8;
 	WriteIo8 (0xCD6, 0x26);
 	Data8   = ReadIo8(0xCD7);
 	Data16  |= Data8;
@@ -138,10 +138,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
 	// Get SB800 MMIO Base (AcpiMmioAddr)
 	WriteIo8(0xCD6, 0x27);
 	Data8 = ReadIo8(0xCD7);
-	Data16=Data8<<8;
+	Data16 = Data8 << 8;
 	WriteIo8(0xCD6, 0x26);
 	Data8 = ReadIo8(0xCD7);
-	Data16|=Data8;
+	Data16 |= Data8;
 	AcpiMmioAddr = (UINT32)Data16 << 16;
 	Status = AGESA_UNSUPPORTED;
 	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c
index 905f6c383c..640f63974e 100644
--- a/src/mainboard/amd/inagua/broadcom.c
+++ b/src/mainboard/amd/inagua/broadcom.c
@@ -73,7 +73,7 @@ void broadcom_init(void);
  * programmed with register 0x5A4 of the MAC. AMD renamed them to "GBE_STAT" and
  * won't say anything about their purpose. Appearently hardware designers are
  * expected to blindly copy the Inagua reference schematic: GBE_STAT2:
- * 0=activity; GBE_STAT[1:0]: 11=no link, 10=10Mbit, 01=100Mbit, 00=1Gbit.
+ * 0 = activity; GBE_STAT[1:0]: 11 = no link, 10 = 10Mbit, 01 = 100Mbit, 00 = 1Gbit.
  *
  * For package processing the 5785 also features a MIPS-based RISC CPU, booting
  * from an internal ROM. The firmware loads config data and supplements (e.g. to
@@ -119,7 +119,7 @@ static struct selfboot_patch {		//Watch out: all values are *BIG-ENDIAN*!
 		u16 basic_config;	//?, see below
 		u8 checksum;		//byte sum of header == 0
 		u8 unknown2;		//?, patch rejected if changed
-		u16 patch_version;	//10-8: major; 7-0: minor; 15-11: variant (1=a, 2=b, ...)
+		u16 patch_version;	//10-8: major; 7-0: minor; 15-11: variant (1 = a, 2 = b, ...)
 	} header;
 
 	struct {	/* Init code */
@@ -197,8 +197,8 @@ static struct selfboot_patch {		//Watch out: all values are *BIG-ENDIAN*!
 	/* Bitfield enabling general features/codepaths in the firmware or
 	 * selecting support for one of several supported PHYs?
 	 * Bits not listed had no appearent effect:
-	 * 14-11: any bit 1=firmware execution seemed delayed
-	 * 10: 0=firmware execution seemed delayed
+	 * 14-11: any bit 1 = firmware execution seemed delayed
+	 * 10: 0 = firmware execution seemed delayed
 	 * 9,2,0: select PHY type, affects these registers, probably more
 	 *  9 2 0 | reg 0x05A4  PHY reg 31  PHY 23,24,28        Notes
 	 * -------+----------------------------------------------------------
@@ -221,7 +221,7 @@ static struct selfboot_patch {		//Watch out: all values are *BIG-ENDIAN*!
 	 * never seen used. Generally, lower values appear to be run earlier.
 	 * An "ifconfig up" with Linux' "tg3" driver causes the tags 0x50, 60,
 	 * 68, 20, 70, 80 to be interpreted in this order.
-	 * All tests were performed with .basic_config=0x0604.
+	 * All tests were performed with .basic_config = 0x0604.
 	 */
 	.init.hunk1_when = 0x10,	//only once at RISC CPU reset?
 	/* Instructions are obviously a specialized bytecode interpreted by the
@@ -250,7 +250,7 @@ static struct selfboot_patch {		//Watch out: all values are *BIG-ENDIAN*!
 		be(0x082B8105),					//CFR-AF: PHY0B: KSZ9021 select PHY105
 		be(0x082C3333),					//CFR-AF: PHY0C: KSZ9021 RX data skew (empirical)
 #endif
-		be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000),	//v1.05 : 5A0.24,12=1: auto-clock-switch
+		be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000),	//v1.05 : 5A0.24,12 = 1: auto-clock-switch
 		be(0x06100D34), be(0x00000000),			//v1.03 : MemD34: clear config vars
 		be(0x06100D38), be(0x00000000),			//v1.03 :    -  |
 		be(0x06100D3C), be(0x00000000),			//v1.03 : MemD3F|
@@ -287,7 +287,7 @@ static struct selfboot_patch {		//Watch out: all values are *BIG-ENDIAN*!
 		be(0x08380000),					//CFR-AF: PHY18|
 		be(0x083C0000),					//CFR-AF: PHY1C|
 #endif
-		be(0xCB0005A4), be(0xF7F0000C),			//v1.01 : if 5A4.0==1 -->skip next 12 bytes
+		be(0xCB0005A4), be(0xF7F0000C),			//v1.01 : if 5A4.0 == 1 -->skip next 12 bytes
 #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF
 		be(0xC61005A4), be(0x3210C500),			//v1.01 : 5A4: PHY LED mode
 #else
@@ -304,9 +304,9 @@ static struct selfboot_patch {		//Watch out: all values are *BIG-ENDIAN*!
 		be(0x083CB001),					//v1.10 : PHY1C: IDDQ B50610 PHY
 #endif
 		be(0xF7F30116),					//        IDDQ PHY
-		be(0xC40005A0),					//v1.09 : 5A0.0=0: Port Mode = MII
-		be(0xC4180400),					//v1.09 : 400.3=0|
-		be(0xC3100400),					//v1.09 : 400.2=1|
+		be(0xC40005A0),					//v1.09 : 5A0.0 = 0: Port Mode = MII
+		be(0xC4180400),					//v1.09 : 400.3 = 0|
+		be(0xC3100400),					//v1.09 : 400.2 = 1|
 	}, //-->PWRDN_LENGTH!
 
 };
@@ -326,10 +326,10 @@ void broadcom_init(void)
 	printk(BIOS_DEBUG, "Upload GbE 'NV'RAM contents @ 0x%08lx\n", (unsigned long)gec_shadow);
 
 	/* Halt RISC CPU before uploading the firmware patch */
-	for (i=10000; i > 0; i--) {
+	for (i = 10000; i > 0; i--) {
 		gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state
-		gec_base[0x5000/4] |= (1<<10);   //issue RISC halt
-		if (gec_base[0x5000/4] | (1<<10))
+		gec_base[0x5000/4] |= (1 << 10);   //issue RISC halt
+		if (gec_base[0x5000/4] | (1 << 10))
 			break;
 		udelay(10);
 	}
diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c
index 511278231e..2c633e5b05 100644
--- a/src/mainboard/amd/lamar/BiosCallOuts.c
+++ b/src/mainboard/amd/lamar/BiosCallOuts.c
@@ -321,10 +321,10 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
 		/* Azalia Controller OEM Codec Table Pointer */
 		FchParams->Azalia.AzaliaPinCfg = TRUE;
 		FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){
-			.AzaliaSdin0 = (CONFIG_AZ_PIN>>0) & 0x03,
-			.AzaliaSdin1 = (CONFIG_AZ_PIN>>2) & 0x03,
-			.AzaliaSdin2 = (CONFIG_AZ_PIN>>4) & 0x03,
-			.AzaliaSdin3 = (CONFIG_AZ_PIN>>6) & 0x03
+			.AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03,
+			.AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03,
+			.AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03,
+			.AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03
 		};
 		FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList;
 		/* Azalia Controller Front Panel OEM Table Pointer */
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
index c627cf5a00..708ddbd4db 100644
--- a/src/mainboard/amd/mahogany/mptable.c
+++ b/src/mainboard/amd/mahogany/mptable.c
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
 			dword = pci_read_config32(dev, 0xac);
 			dword &= ~(7 << 26);
 			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1<<22; PIC and APIC co exists */
+			/* dword |= 1 << 22; PIC and APIC co exists */
 			pci_write_config32(dev, 0xac, dword);
 
 			/*
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 662e7cfd12..1e0000e877 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -110,7 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	cpuid1 = cpuid(0x80000007);
 	if ((cpuid1.edx & 0x6) == 0x6) {
 		/* Read FIDVID_STATUS */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
@@ -118,7 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		init_fidvid_bsp(bsp_apicid);
 
 		/* show final fid and vid */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 	} else {
 		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index 4c74e4ef7e..3f9d7c7f94 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
 			dword = pci_read_config32(dev, 0xac);
 			dword &= ~(7 << 26);
 			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1<<22; PIC and APIC co exists */
+			/* dword |= 1 << 22; PIC and APIC co exists */
 			pci_write_config32(dev, 0xac, dword);
 
 			/*
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 3428aab9ab..1ee6698d70 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3A);
 
 	/* show final fid and vid */
-	msr=rdmsr(0xc0010071);
+	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
  #endif
 
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index 9a2a9bb458..b0b79ab2c8 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -63,10 +63,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
 	// Get SB800 MMIO Base (AcpiMmioAddr)
 	WriteIo8(0xCD6, 0x27);
 	Data8 = ReadIo8(0xCD7);
-	Data16=Data8<<8;
+	Data16 = Data8 << 8;
 	WriteIo8(0xCD6, 0x26);
 	Data8 = ReadIo8(0xCD7);
-	Data16|=Data8;
+	Data16 |= Data8;
 	AcpiMmioAddr = (UINT32)Data16 << 16;
 	Status = AGESA_UNSUPPORTED;
 	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c
index f9768b20bd..b397f52aea 100644
--- a/src/mainboard/amd/pistachio/fadt.c
+++ b/src/mainboard/amd/pistachio/fadt.c
@@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 
 	fadt->firmware_ctrl = (u32) facs;
 	fadt->dsdt = (u32) dsdt;
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
 	fadt->preferred_pm_profile = 0x03;
 	fadt->sci_int = 9;
 	/* disable system management mode by setting to 0: */
@@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
 	pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
 
-	pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
+	pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
 					* the contents of the PM registers at
 					* index 20-2B to decode ACPI I/O address.
 					* AcpiSmiEn & SmiCmdEn*/
-	pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
 	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
 
 	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
index 261ac9ad4b..76ee05681f 100644
--- a/src/mainboard/amd/pistachio/mptable.c
+++ b/src/mainboard/amd/pistachio/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
 			dword = pci_read_config32(dev, 0xac);
 			dword &= ~(7 << 26);
 			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1<<22; PIC and APIC co exists */
+			/* dword |= 1 << 22; PIC and APIC co exists */
 			pci_write_config32(dev, 0xac, dword);
 
 			/*
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index c78f0d24a6..549ad0ceac 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -112,7 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	cpuid1 = cpuid(0x80000007);
 	if ((cpuid1.edx & 0x6) == 0x6) {
 		/* Read FIDVID_STATUS */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
 		enable_fid_change();
@@ -120,7 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		init_fidvid_bsp(bsp_apicid);
 
 		/* show final fid and vid */
-		msr=rdmsr(0xc0010042);
+		msr = rdmsr(0xc0010042);
 		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 	} else {
 		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
diff --git a/src/mainboard/amd/rumba/irq_tables.c b/src/mainboard/amd/rumba/irq_tables.c
index 1ef4f5fa8d..41f04067c9 100644
--- a/src/mainboard/amd/rumba/irq_tables.c
+++ b/src/mainboard/amd/rumba/irq_tables.c
@@ -36,7 +36,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_VERSION,    /* u16 version   */
 	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x12<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	(0x12 << 3)|0x0,   /* Where the interrupt router lies (dev) */
 	0x800,		 /* IRQs devoted exclusively to PCI usage */
 	0x1078,		 /* Vendor */
 	0x2,		 /* Device */
@@ -44,9 +44,9 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0xdf,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
-		{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x0e << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
+		{0x00,(0x0f << 3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
 	}
 };
 unsigned long write_pirq_routing_table(unsigned long addr)
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
index f75f8208f6..ddc232f03f 100644
--- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
@@ -37,7 +37,7 @@
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
-	u32 gsi_base=0x18;
+	u32 gsi_base = 0x18;
 
 	struct mb_sysconf_t *m;
 
@@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 		int i;
 		int j = 0;
 
-		for(i=1; i< sysconf.hc_possible_num; i++) {
+		for(i = 1; i< sysconf.hc_possible_num; i++) {
 			u32 d = 0;
 			if(!(sysconf.pci1234[i] & 0x1) ) continue;
 			// 8131 need to use +4
@@ -149,11 +149,11 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp
 
 	//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
 
-	for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
+	for(i = 1; i < sysconf.hc_possible_num; i++) {  // 0: is hc sblink
 		const char *file_name;
 		if((sysconf.pci1234[i] & 1) != 1 ) continue;
 		u8 c;
-		if(i<7) {
+		if(i < 7) {
 			c  = (u8) ('4' + i - 1);
 		}
 		else {
diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c
index bd0096152b..6bb03e92e7 100644
--- a/src/mainboard/amd/serengeti_cheetah/fadt.c
+++ b/src/mainboard/amd/serengeti_cheetah/fadt.c
@@ -37,13 +37,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 	memcpy(header->oem_id,OEM_ID,6);
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id,ASLC,4);
-	header->asl_compiler_revision=0;
+	header->asl_compiler_revision = 0;
 
 	fadt->firmware_ctrl=(u32)facs;
 	fadt->dsdt= (u32)dsdt;
-	// 3=Workstation,4=Enterprise Server, 7=Performance Server
-	fadt->preferred_pm_profile=0x03;
-	fadt->sci_int=9;
+	// 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
 	// disable system management mode by setting to 0:
 	fadt->smi_cmd = 0;//pm_base+0x2f;
 	fadt->acpi_enable = 0xf0;
diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c
index 2fc3ee6334..3d9820f542 100644
--- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c
@@ -124,7 +124,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	slot_num++;
 
 //pcix bridge
-//        write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+//        write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 //        pirq_info++; slot_num++;
 
 	int j = 0;
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 8236e7baa3..acc4a6c68c 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v)
 
                 j = 0;
 
-                for(i=1; i< sysconf.hc_possible_num; i++) {
+                for(i = 1; i< sysconf.hc_possible_num; i++) {
                         if(!(sysconf.pci1234[i] & 0x1) ) continue;
 
                         switch(sysconf.hcid[i]) {
@@ -101,34 +101,34 @@ static void *smp_write_config_table(void *v)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
 
 // Onboard AMD USB
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
 
 //Slot 3  PCI 32
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
         }
 
 
 //Slot 4 PCI 32
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
         }
 
 
 //Slot 1 PCI-X 133/100/66
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); //
         }
 
 
 //Slot 2 PCI-X 133/100/66
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
         }
 
         j = 0;
 
-        for(i=1; i< sysconf.hc_possible_num; i++) {
+        for(i = 1; i< sysconf.hc_possible_num; i++) {
                 if(!(sysconf.pci1234[i] & 0x1) ) continue;
                 int ii;
                 device_t dev;
@@ -141,8 +141,8 @@ static void *smp_write_config_table(void *v)
                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
                                 if (res) {
                                         //Slot 1 PCI-X 133/100/66
-                                        for(ii=0;ii<4;ii++) {
-                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
+                                        for(ii = 0; ii < 4; ii++) {
+                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
                                         }
                                 }
                         }
@@ -152,8 +152,8 @@ static void *smp_write_config_table(void *v)
                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
                                 if (res) {
                                         //Slot 2 PCI-X 133/100/66
-                                        for(ii=0;ii<4;ii++) {
-                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
+                                        for(ii = 0; ii < 4; ii++) {
+                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
                                         }
                                 }
                         }
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 51fce316a7..53adf6c274 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -38,8 +38,8 @@
 static void memreset_setup(void)
 {
 	//GPIO on amd8111 to enable MEMRST ????
-        outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-        outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+        outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN = 1
+        outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -49,11 +49,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
 #define SMBUS_HUB 0x18
         int ret,i;
         unsigned device=(ctrl->channel0[0])>>8;
-        /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
-        i=2;
+        /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
+        i = 2;
         do {
                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-        } while ((ret!=0) && (i-->0));
+        } while ((ret != 0) && (i-->0));
 
         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 }
@@ -74,10 +74,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#define RC0 ((1<<0)<<8)
-#define RC1 ((1<<1)<<8)
-#define RC2 ((1<<2)<<8)
-#define RC3 ((1<<3)<<8)
+#define RC0 ((1 << 0)<<8)
+#define RC1 ((1 << 1)<<8)
+#define RC2 ((1 << 2)<<8)
+#define RC3 ((1 << 3)<<8)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
 		/* Read FIDVID_STATUS */
                 msr_t msr;
-                msr=rdmsr(0xc0010042);
+                msr = rdmsr(0xc0010042);
                 printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         // show final fid and vid
         {
                 msr_t msr;
-                msr=rdmsr(0xc0010042);
+                msr = rdmsr(0xc0010042);
                 printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 
@@ -200,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 #if 0
 	int i;
-	for(i=0;i<4;i++) {
+	for(i = 0; i < 4; i++) {
 		activate_spd_rom(&cpu[i]);
 		dump_smbus_registers();
 	}
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
index 7496a60e7d..d7aaff2061 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
@@ -29,7 +29,7 @@
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
-	u32 gsi_base=0x18;
+	u32 gsi_base = 0x18;
 
 	struct mb_sysconf_t *m;
 
@@ -69,7 +69,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 		int i;
 		int j = 0;
 
-		for(i=1; i< sysconf.hc_possible_num; i++) {
+		for(i = 1; i < sysconf.hc_possible_num; i++) {
 			u32 d = 0;
 			if(!(sysconf.pci1234[i] & 0x1) ) continue;
 			// 8131 need to use +4
@@ -138,11 +138,11 @@ unsigned long mainboard_write_acpi_tables(device_t device,
 	/* same htio, but different possition? We may have to copy,
 	change HCIN, and recalculate the checknum and add_table */
 
-	for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
+	for(i = 1; i < sysconf.hc_possible_num; i++) {  // 0: is hc sblink
 		const char *file_name;
 		if((sysconf.pci1234[i] & 1) != 1 ) continue;
 		u8 c;
-		if(i<7) {
+		if(i < 7) {
 			c  = (u8) ('4' + i - 1);
 		}
 		else {
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
index 3183a7ebcc..7f54896c30 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
@@ -40,13 +40,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 	memcpy(header->oem_id,OEM_ID,6);
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id,ASLC,4);
-	header->asl_compiler_revision=0;
+	header->asl_compiler_revision = 0;
 
 	fadt->firmware_ctrl=(u32)facs;
 	fadt->dsdt= (u32)dsdt;
-	// 3=Workstation,4=Enterprise Server, 7=Performance Server
-	fadt->preferred_pm_profile=0x03;
-	fadt->sci_int=9;
+	// 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
 	// disable system management mode by setting to 0:
 	fadt->smi_cmd = 0;//pm_base+0x2f;
 	fadt->acpi_enable = 0xf0;
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
index 66dee1831d..87ca67274f 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
@@ -103,7 +103,7 @@ void get_bus_conf(void)
 	m = sysconf.mb;
 
 	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-	for(i=0;i<sysconf.hc_possible_num; i++) {
+	for(i = 0; i < sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];
 	}
@@ -141,8 +141,8 @@ void get_bus_conf(void)
 	}
 
 	 /* HT chain 1 */
-	j=0;
-	for(i=1; i< sysconf.hc_possible_num; i++) {
+	j = 0;
+	for(i = 1; i< sysconf.hc_possible_num; i++) {
 		if(!(sysconf.pci1234[i] & 0x1) ) continue;
 
 		// check hcid type here
@@ -199,7 +199,7 @@ void get_bus_conf(void)
 	m->apicid_8111 = apicid_base + 0;
 	m->apicid_8132_1 = apicid_base + 1;
 	m->apicid_8132_2 = apicid_base + 2;
-	for(i=0;i<j;i++) {
+	for(i = 0; i < j; i++) {
 		m->apicid_8132a[i][0] = apicid_base + 3 + i * 2;
 		m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1;
 	}
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
index 380510da4e..4bb03c7dc6 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c
@@ -94,7 +94,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	slot_num++;
 
 	//pcix bridge
-//      write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+//      write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 //      pirq_info++; slot_num++;
 
 	int j = 0;
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index 7b2e22efb2..8699294f59 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -67,7 +67,7 @@ static void *smp_write_config_table(void *v)
 
 		j = 0;
 
-		for(i=1; i< sysconf.hc_possible_num; i++) {
+		for(i = 1; i< sysconf.hc_possible_num; i++) {
 			if(!(sysconf.pci1234[i] & 0x1) ) continue;
 
 			switch(sysconf.hcid[i]) {
@@ -103,34 +103,34 @@ static void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
 
 	// Onboard AMD USB
-	 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
+	 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
 
 	//Slot 3  PCI 32
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
 	}
 
 
 	// Slot 4 PCI 32
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
 	}
 
 
 	// Slot 1 PCI-X 133/100/66
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); //
 	}
 
 
 	//Slot 2 PCI-X 133/100/66
-	for(i=0;i<4;i++) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
+	for(i = 0; i < 4; i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
 	}
 
 	j = 0;
 
-	for(i=1; i< sysconf.hc_possible_num; i++) {
+	for(i = 1; i< sysconf.hc_possible_num; i++) {
 		if(!(sysconf.pci1234[i] & 0x1) ) continue;
 		int ii;
 		int jj;
@@ -143,10 +143,10 @@ static void *smp_write_config_table(void *v)
 			if (dev) {
 				res = find_resource(dev, PCI_BASE_ADDRESS_0);
 				if (res) {
-					for(jj=0; jj<4; jj++) {
+					for(jj = 0; jj < 4; jj++) {
 						//Slot 1 PCI-X 133/100/66
-						for(ii=0;ii<4;ii++) {
-							smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
+						for(ii = 0; ii < 4; ii++) {
+							smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
 						}
 					}
 				}
@@ -156,10 +156,10 @@ static void *smp_write_config_table(void *v)
 			if (dev) {
 				res = find_resource(dev, PCI_BASE_ADDRESS_0);
 				if (res) {
-					for(jj=0; jj<4; jj++) {
+					for(jj = 0; jj < 4; jj++) {
 						//Slot 2 PCI-X 133/100/66
-						for(ii=0;ii<4;ii++) {
-							smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
+						for(ii = 0; ii < 4; ii++) {
+							smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
 						}
 					}
 				}
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 0c84b6d1e0..1ccdf268c7 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -51,8 +51,8 @@
 static void memreset_setup(void)
 {
 	//GPIO on amd8111 to enable MEMRST ????
-	outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);	// REVC_MEMRST_EN=1
-	outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+	outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16);	// REVC_MEMRST_EN = 1
+	outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void activate_spd_rom(const struct mem_controller *ctrl)
@@ -63,11 +63,11 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
 
 	printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id);
 
-	/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
-	i=2;
+	/* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
+	i = 2;
 	do {
 		ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7)));
-	} while ((ret!=0) && (i-->0));
+	} while ((ret != 0) && (i-->0));
 	smbus_write_byte(SMBUS_HUB, 0x03, 0);
 }
 
@@ -277,7 +277,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3A);
 
 	/* show final fid and vid */
-	msr=rdmsr(0xc0010071);
+	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
  #endif
 
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c
index e68db1362f..711a0d5427 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.c
+++ b/src/mainboard/amd/south_station/BiosCallOuts.c
@@ -57,7 +57,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
   /* Get SB MMIO Base (AcpiMmioAddr) */
   WriteIo8 (0xCD6, 0x27);
   Data8   = ReadIo8(0xCD7);
-  Data16  = Data8<<8;
+  Data16  = Data8 << 8;
   WriteIo8 (0xCD6, 0x26);
   Data8   = ReadIo8(0xCD7);
   Data16  |= Data8;
@@ -138,10 +138,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
   // Get SB800 MMIO Base (AcpiMmioAddr)
   WriteIo8(0xCD6, 0x27);
   Data8 = ReadIo8(0xCD7);
-  Data16=Data8<<8;
+  Data16 = Data8 << 8;
   WriteIo8(0xCD6, 0x26);
   Data8 = ReadIo8(0xCD7);
-  Data16|=Data8;
+  Data16 |= Data8;
   AcpiMmioAddr = (UINT32)Data16 << 16;
   Status = AGESA_UNSUPPORTED;
   GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index 4c74e4ef7e..3f9d7c7f94 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
 			dword = pci_read_config32(dev, 0xac);
 			dword &= ~(7 << 26);
 			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1<<22; PIC and APIC co exists */
+			/* dword |= 1 << 22; PIC and APIC co exists */
 			pci_write_config32(dev, 0xac, dword);
 
 			/*
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 68281e7455..1faac4d73f 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3A);
 
 	/* show final fid and vid */
-	msr=rdmsr(0xc0010071);
+	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c
index 6f5e0a9d0f..b64cef37c0 100644
--- a/src/mainboard/amd/torpedo/BiosCallOuts.c
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.c
@@ -58,7 +58,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
   /* Get SB MMIO Base (AcpiMmioAddr) */
   WriteIo8 (0xCD6, 0x27);
   Data8   = ReadIo8(0xCD7);
-  Data16  = Data8<<8;
+  Data16  = Data8 << 8;
   WriteIo8 (0xCD6, 0x26);
   Data8   = ReadIo8(0xCD7);
   Data16  |= Data8;
@@ -108,10 +108,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
   // Get SB MMIO Base (AcpiMmioAddr)
   WriteIo8(0xCD6, 0x27);
   Data8 = ReadIo8(0xCD7);
-  Data16=Data8<<8;
+  Data16 = Data8 << 8;
   WriteIo8(0xCD6, 0x26);
   Data8 = ReadIo8(0xCD7);
-  Data16|=Data8;
+  Data16 |= Data8;
   AcpiMmioAddr = (UINT32)Data16 << 16;
   Status = AGESA_UNSUPPORTED;
   GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c
index fba8fc83cd..b20cfc8fb4 100644
--- a/src/mainboard/amd/torpedo/fadt.c
+++ b/src/mainboard/amd/torpedo/fadt.c
@@ -66,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	else
 		fadt->dsdt = (uintptr_t)dsdt;
 
-	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	/* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
 	fadt->preferred_pm_profile = 0x03;
 	fadt->sci_int = 9;
 	/* disable system management mode by setting to 0: */
diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c
index b9fe745e18..ac98557175 100644
--- a/src/mainboard/amd/torpedo/gpio.c
+++ b/src/mainboard/amd/torpedo/gpio.c
@@ -177,7 +177,7 @@ gpioEarlyInit(
 		RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1);      // GPIO
 		RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5);    // GPI
 
-		// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW)
+		// set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW)
 		RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
 		RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
 		RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
@@ -355,7 +355,7 @@ gpioEarlyInit(
 		}
 //		else
 //		{ // 0 - AUTO
-//			// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable)
+//			// set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable)
 //			RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
 //			RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
 //		}
@@ -375,7 +375,7 @@ gpioEarlyInit(
 		}
 //		else
 //		{ // 0 - AUTO
-//			// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)
+//			// set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH)
 //			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
 //			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
 //
diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h
index f5decb3503..f2ceb02d43 100644
--- a/src/mainboard/amd/torpedo/gpio.h
+++ b/src/mainboard/amd/torpedo/gpio.h
@@ -341,8 +341,8 @@
 #define GPIO_228_SELECT     FUNCTION0+NonGpio   // SMBUS, DATA
 #define GPIO_229_SELECT     FUNCTION0+NonGpio   // DP1_HPD
 
-#define TYPE_GPI  (1<<5)
-#define TYPE_GPO  (0<<5)
+#define TYPE_GPI  (1 << 5)
+#define TYPE_GPO  (0 << 5)
 
 #define GPIO_00_TYPE        TYPE_GPO
 #define GPIO_01_TYPE        TYPE_GPO
@@ -578,8 +578,8 @@
 #define GPIO_228_TYPE       TYPE_GPO
 #define GPIO_229_TYPE       TYPE_GPO
 
-#define GPO_LOW   (0<<6)
-#define GPO_HI    (1<<6)
+#define GPO_LOW   (0 << 6)
+#define GPO_HI    (1 << 6)
 
 #define GPO_00_LEVEL        GPO_HI
 #define GPO_01_LEVEL        GPO_HI
@@ -812,8 +812,8 @@
 #define GPO_228_LEVEL       GPO_LOW
 #define GPO_229_LEVEL       GPO_LOW
 
-#define GPIO_NONSTICKY   (0<<2)
-#define GPIO_STICKY      (1<<2)
+#define GPIO_NONSTICKY   (0 << 2)
+#define GPIO_STICKY      (1 << 2)
 
 #define GPIO_00_STICKY      GPIO_NONSTICKY
 #define GPIO_01_STICKY      GPIO_NONSTICKY
@@ -1046,8 +1046,8 @@
 #define GPIO_228_STICKY     GPIO_NONSTICKY
 #define GPIO_229_STICKY     GPIO_NONSTICKY
 
-#define PULLUP_ENABLE      (0<<3)
-#define PULLUP_DISABLE     (1<<3)
+#define PULLUP_ENABLE      (0 << 3)
+#define PULLUP_DISABLE     (1 << 3)
 
 #define GPIO_00_PULLUP      PULLUP_DISABLE
 #define GPIO_01_PULLUP      PULLUP_DISABLE
@@ -1282,8 +1282,8 @@
 #define GPIO_228_PULLUP     PULLUP_DISABLE
 #define GPIO_229_PULLUP     PULLUP_DISABLE
 
-#define PULLDOWN_ENABLE       (1<<4)
-#define PULLDOWN_DISABLE      (0<<4)
+#define PULLDOWN_ENABLE       (1 << 4)
+#define PULLDOWN_DISABLE      (0 << 4)
 
 #define GPIO_00_PULLDOWN    PULLDOWN_DISABLE
 #define GPIO_01_PULLDOWN    PULLDOWN_DISABLE
@@ -1750,7 +1750,7 @@
 
 typedef enum _GPIO_COUNT
 {
-    GPIO_00=0,
+    GPIO_00 = 0,
     GPIO_01,
     GPIO_02,
     GPIO_03,
@@ -2227,7 +2227,7 @@ const GPIO_SETTINGS gpio_table[]=
 
 typedef enum _GEVENT_COUNT
 {
-    GEVENT_00=0x60,
+    GEVENT_00 = 0x60,
     GEVENT_01,
     GEVENT_02,
     GEVENT_03,
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
index e68db1362f..711a0d5427 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.c
+++ b/src/mainboard/amd/union_station/BiosCallOuts.c
@@ -57,7 +57,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
   /* Get SB MMIO Base (AcpiMmioAddr) */
   WriteIo8 (0xCD6, 0x27);
   Data8   = ReadIo8(0xCD7);
-  Data16  = Data8<<8;
+  Data16  = Data8 << 8;
   WriteIo8 (0xCD6, 0x26);
   Data8   = ReadIo8(0xCD7);
   Data16  |= Data8;
@@ -138,10 +138,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
   // Get SB800 MMIO Base (AcpiMmioAddr)
   WriteIo8(0xCD6, 0x27);
   Data8 = ReadIo8(0xCD7);
-  Data16=Data8<<8;
+  Data16 = Data8 << 8;
   WriteIo8(0xCD6, 0x26);
   Data8 = ReadIo8(0xCD7);
-  Data16|=Data8;
+  Data16 |= Data8;
   AcpiMmioAddr = (UINT32)Data16 << 16;
   Status = AGESA_UNSUPPORTED;
   GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;