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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-04-11 12:19:03 +0300 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-04-12 10:27:34 +0200 |
| commit | 3aff1a32087137169fb4165eb2dd11655de27f45 (patch) | |
| tree | f355095bdb44c137fb2de9eece16e8f366ebe9ff /src/mainboard/aopen/dxplplusu/Kconfig | |
| parent | eb59636cc5875bac98a949f206e5f8c0462be238 (diff) | |
| download | coreboot-3aff1a32087137169fb4165eb2dd11655de27f45.tar.xz | |
Convert AOpen DXPL Plus mainboard to CAR
Tested on real hardware, mainboard with dual Xeon P4 HT CPUs
requires cache-as-ram init code with AP SIPI protocol.
Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI.
Change-Id: I415482f3af22df79d82492c49aed83549f29aa56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/aopen/dxplplusu/Kconfig')
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/Kconfig | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index c3025d157a..da03491d87 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -8,8 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_LPC47M10X - select ROMCC - select HAVE_HARD_RESET # select HAVE_PIRQ_TABLE # select PIRQ_ROUTE select UDELAY_TSC @@ -24,14 +22,6 @@ config MAINBOARD_PART_NUMBER string default "DXPL Plus-U" -config DCACHE_RAM_BASE - hex - default 0xcf000 - -config DCACHE_RAM_SIZE - hex - default 0x1000 - config IRQ_SLOT_COUNT int default 12 @@ -40,18 +30,10 @@ config BOARD_HAS_FADT bool default y -config LOGICAL_CPUS - bool - default n - config MAX_CPUS int default 4 -config MAX_PHYSICAL_CPUS - int - default 2 - config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x0 |