diff options
| author | Furquan Shaikh <furquan@google.com> | 2018-06-19 08:40:19 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-06-20 18:28:46 +0000 |
| commit | faad9684a9882c6521913872d39222221e6c871a (patch) | |
| tree | c824931fc7067859dcb050536f11d4e39ddf30eb /src/mainboard/aopen/dxplplusu | |
| parent | d4d1ef81893175ef68a377392af6d5b8d1c2d7dc (diff) | |
| download | coreboot-faad9684a9882c6521913872d39222221e6c871a.tar.xz | |
mb/google/octopus: Configure EC_IN_RW correctly
This change fixes the following issues with EC_IN_RW signal:
1. EC_IN_RW is an input signal to the SoC. Configure it accordingly in
GPIO table for baseboard and bip.
2. GPIO_EC_IN_RW is passed in coreboot tables so that payload can
re-sample the GPIO at runtime.
BUG=b:110084012
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.
Change-Id: I1c5f5b4b914ced98e89a571dc398df5ba1fe8460
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'src/mainboard/aopen/dxplplusu')
0 files changed, 0 insertions, 0 deletions