summaryrefslogtreecommitdiff
path: root/src/mainboard/aopen
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-07 11:00:50 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-12 16:02:55 +0000
commit61af679838ab52318641828b6a77c81229033c77 (patch)
tree36ea549af8cd0c6ffa5dbca29c318196b0e43dac /src/mainboard/aopen
parent9e581ec2264b39e7268fdf1dbcaaa82705111df9 (diff)
downloadcoreboot-61af679838ab52318641828b6a77c81229033c77.tar.xz
aopen/dxplplusu,intel/e7505: Move mainboard_romstage_entry()
Change-Id: I15aaefdf0c81f58adfeb6f4dde2f05b3c06fd145 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/aopen')
-rw-r--r--src/mainboard/aopen/dxplplusu/romstage.c49
1 files changed, 0 insertions, 49 deletions
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c
deleted file mode 100644
index 6c74c1febf..0000000000
--- a/src/mainboard/aopen/dxplplusu/romstage.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <arch/romstage.h>
-
-#include <southbridge/intel/i82801dx/i82801dx.h>
-#include <northbridge/intel/e7505/raminit.h>
-
-void mainboard_romstage_entry(void)
-{
- static const struct mem_controller memctrl[] = {
- {
- .d0 = PCI_DEV(0, 0, 0),
- .d0f1 = PCI_DEV(0, 0, 1),
- .channel0 = { 0x50, 0x52, 0, 0 },
- .channel1 = { 0x51, 0x53, 0, 0 },
- },
- };
-
- /* If this is a warm boot, some initialization can be skipped */
- if (!e7505_mch_is_ready()) {
- enable_smbus();
-
- /* The real MCH initialisation. */
- e7505_mch_init(memctrl);
-
- /* Hook for post ECC scrub settings and debug. */
- e7505_mch_done(memctrl);
- }
-
- printk(BIOS_DEBUG, "SDRAM is up.\n");
-
- cbmem_recovery(0);
-}