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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-19 17:09:01 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-20 18:59:19 +0000
commit4d991550b3a38346071da9dbdc0e7e96a6076082 (patch)
treecbc9e635967fa5ce9b01959a8c15565b86edf042 /src/mainboard/aopen
parentfaad9684a9882c6521913872d39222221e6c871a (diff)
downloadcoreboot-4d991550b3a38346071da9dbdc0e7e96a6076082.tar.xz
aopen/dxplplusu: Add romstage timestamps
Change-Id: Ic6e2a350a976a3fcb421d47a0bf5600df994edc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/aopen')
-rw-r--r--src/mainboard/aopen/dxplplusu/romstage.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c
index 6ea1261231..f203dd1f72 100644
--- a/src/mainboard/aopen/dxplplusu/romstage.c
+++ b/src/mainboard/aopen/dxplplusu/romstage.c
@@ -22,6 +22,7 @@
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
+#include <timestamp.h>
#include <southbridge/intel/i82801dx/i82801dx.h>
#include <northbridge/intel/e7505/raminit.h>
@@ -47,6 +48,9 @@ void mainboard_romstage_entry(unsigned long bist)
},
};
+ timestamp_init(timestamp_get());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
/* Get the serial port running and print a welcome banner */
lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
@@ -58,6 +62,8 @@ void mainboard_romstage_entry(unsigned long bist)
if (!e7505_mch_is_ready()) {
enable_smbus();
+ timestamp_add_now(TS_BEFORE_INITRAM);
+
/* The real MCH initialisation. */
e7505_mch_init(memctrl);
@@ -75,6 +81,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Hook for post ECC scrub settings and debug. */
e7505_mch_done(memctrl);
+
+ timestamp_add_now(TS_AFTER_INITRAM);
}
printk(BIOS_DEBUG, "SDRAM is up.\n");