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authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-04-10 19:55:19 +0300
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-04-11 23:25:09 +0200
commit5c1ff9284a7ac382a9ec702fa52f3a173279d566 (patch)
treeff8d7d75c484aedeb4337621670e4a406f799e4b /src/mainboard/aopen
parent5bd271b9fa81532f786f42604d94df92f44b605f (diff)
downloadcoreboot-5c1ff9284a7ac382a9ec702fa52f3a173279d566.tar.xz
Intel e7505: cleanups
Fix delay loop comments. Time waited and the comments did not match in the origin (e7501), so delays currently "just work". Move reset detection to main raminit and don't use generic sdram_initialize for now, as there are local debug functions I need to use. Fix AOpen respectively. Disable ecc scrub, until I have it fixed for cache-as-ram use. Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/883 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/aopen')
-rw-r--r--src/mainboard/aopen/dxplplusu/romstage.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c
index 92ce8961d4..573e0f1880 100644
--- a/src/mainboard/aopen/dxplplusu/romstage.c
+++ b/src/mainboard/aopen/dxplplusu/romstage.c
@@ -62,8 +62,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#endif
#include "northbridge/intel/e7505/raminit.c"
-#include "northbridge/intel/e7505/reset_test.c"
-#include "lib/generic_sdram.c"
// This function MUST appear last (ROMCC limitation)
BOARD_MAIN(unsigned long bist)