diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-17 14:16:03 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-02 21:55:31 +0000 |
| commit | 717b6e3151b6ea42aaa4b1ab2a708e143d098878 (patch) | |
| tree | f7caeb3a85a4cc965e62ca5ddf31217751976178 /src/mainboard/aopen | |
| parent | 9e69c87317794219d7238eb87edc5e23e03803b4 (diff) | |
| download | coreboot-717b6e3151b6ea42aaa4b1ab2a708e143d098878.tar.xz | |
aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INIT
With implementation of LATE_CBMEM_INIT, top-of-low-memory
TOLM was adjusted late in ramstage. We do not allow that with
EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO
space is now used with statically set TOLM.
Also remove support code for the obsolete LATE_CBMEM_INIT
this northbridge used.
Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/aopen')
| -rw-r--r-- | src/mainboard/aopen/dxplplusu/romstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index f79d3d3c92..6ea1261231 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <arch/cpu.h> #include <stdlib.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> @@ -77,4 +78,6 @@ void mainboard_romstage_entry(unsigned long bist) } printk(BIOS_DEBUG, "SDRAM is up.\n"); + + cbmem_recovery(0); } |