sb/ich7: Use common/gpio.h to set up GPIOs

This is more consistent with newer Intel targets.

This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
  is ignored in native mode;
* only output pins are set high or low, since this is read-only on
  input;
* blink is only operational on output pins, non-blink is not set
  explicitly;
* invert is only operational on input pins, non-invert is not set
  explicitly.

Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17639
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

3 files changed, 123 insertions, 52 deletions

diff --git a/src/mainboard/apple/macbook21/Makefile.inc b/src/mainboard/apple/macbook21/Makefile.inc
new file mode 100644
index 0000000000..60484097e9
--- /dev/null
+++ b/src/mainboard/apple/macbook21/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += gpio.c
\ No newline at end of file
diff --git a/src/mainboard/apple/macbook21/gpio.c b/src/mainboard/apple/macbook21/gpio.c
new file mode 100644
index 0000000000..53c5c96ebc
--- /dev/null
+++ b/src/mainboard/apple/macbook21/gpio.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_GPIO,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_GPIO,
+	.gpio26 = GPIO_MODE_GPIO,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_OUTPUT,
+	.gpio6 = GPIO_DIR_OUTPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio9 = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_OUTPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio25 = GPIO_DIR_INPUT,
+	.gpio26 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21)
+	.gpio5 = GPIO_LEVEL_LOW,
+#else /* CONFIG_BOARD_APPLE_IMAC52 */
+	.gpio5 = GPIO_LEVEL_HIGH,
+#endif
+	.gpio6 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_LOW,
+	.gpio14 = GPIO_LEVEL_HIGH,
+	.gpio22 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio7 = GPIO_INVERT,
+#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21)
+	.gpio13 = GPIO_INVERT,
+#endif
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+#if CONFIG_BOARD_APPLE_IMAC52
+	.gpio35 = GPIO_MODE_GPIO,
+#endif
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio48 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+#if CONFIG_BOARD_APPLE_IMAC52
+	.gpio35 = GPIO_DIR_OUTPUT,
+#endif
+	.gpio38 = GPIO_DIR_OUTPUT,
+	.gpio39 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+#if CONFIG_BOARD_APPLE_IMAC52
+	.gpio35 = GPIO_LEVEL_LOW,
+#endif
+	.gpio38 = GPIO_LEVEL_HIGH,
+	.gpio39 = GPIO_LEVEL_HIGH,
+	.gpio48 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+	},
+};
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 391b09f6b7..962ad41577 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -35,58 +35,6 @@
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 
-void setup_ich7_gpios(void)
-{
-	printk(BIOS_DEBUG, " GPIOS...");
-
-	/* X60 GPIO:
-	 * 1: HDD_PRESENCE#
-	 * 6: Unknown (Pulled high by R215 to VCC3B)
-	 * 7: BDC_PRESENCE#
-	 * 8: H8_WAKE#
-	 * 9: RTC_BAT_IN#
-	 * 10: Unknown (Pulled high by R700 to VCC3M)
-	 * 12: H8SCI#
-	 * 13: SLICE_ON_3M#
-	 * 14: Unknown (Pulled high by R321 to VCC3)
-	 * 15: Unknown (Pulled high by R258 to VCC3)
-	 * 19: Unknown (Pulled low  by R594)
-	 * 21: Unknown (Pulled high by R145 to VCC3)
-	 * 22: FWH_WP#
-	 * 25: MDC_KILL#
-	 * 33: HDD_PRESENCE_2#
-	 * 35: CLKREQ_SATA#
-	 * 36: PLANARID0
-	 * 37: PLANARID1
-	 * 38: PLANARID2
-	 * 39: PLANARID3
-	 * 48: FWH_TBL#
-	 */
-#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21)
-	outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
-	outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
-	outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
-	/* Output Control Registers */
-	outl(0x00000000, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
-	/* Input Control Registers */
-	outl(0x00002082, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
-	outl(0x000100c0, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
-	outl(0x00000030, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
-	outl(0x000100c0, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL2 */
-#else /* CONFIG_BOARD_APPLE_IMAC52 */
-	outl(0x1f40f7c2, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
-	outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
-	outl(0xfcc06bff, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
-	/* Output Control Registers */
-	outl(0x00000000, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
-	/* Input Control Registers */
-	outl(0x00000082, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
-	outl(0x000100c8, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
-	outl(0x00000030, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
-	outl(0x000100c0, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL2 */
-#endif
-}
-
 static void ich7_enable_lpc(void)
 {
 	/* Enable Serial IRQ */