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| author | Patrick Rudolph <siro@das-labor.org> | 2016-06-09 18:13:34 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-12 12:48:44 +0200 |
| commit | 266a1f794dc28053e97794cbeb3f1a588137698b (patch) | |
| tree | 7cb11796fa351bd50d15af6be9508a15be223192 /src/mainboard/apple/macbookair4_2/devicetree.cb | |
| parent | e7f35cd2924de7c9b2e8a74a50d35928b9da76a4 (diff) | |
| download | coreboot-266a1f794dc28053e97794cbeb3f1a588137698b.tar.xz | |
nb/intel/raminit (native): Read PCI mmio size from devicetree
Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.
Tested on Sandybridge Lenovo T520.
Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/apple/macbookair4_2/devicetree.cb')
| -rw-r--r-- | src/mainboard/apple/macbookair4_2/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index a43b9f2dc7..226ec04004 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -30,6 +30,9 @@ chip northbridge/intel/sandybridge end end end + + register "pci_mmio_size" = "2048" + device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" |