A new port apple/macbook21.

Current problems:
- Complete lack of EC support (no battery indicator, no temperature, ...)
- No audio support

Change-Id: I25d09629dd82e01fadca2b6c25f72aaf08eafae1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Axel Holewa <mono@posteo.de>
Reviewed-on: http://review.coreboot.org/5321
Tested-by: build bot (Jenkins)

24 files changed, 2028 insertions, 0 deletions

diff --git a/src/mainboard/apple/Kconfig b/src/mainboard/apple/Kconfig
new file mode 100644
index 0000000000..09eb2b55ba
--- /dev/null
+++ b/src/mainboard/apple/Kconfig
@@ -0,0 +1,19 @@
+if VENDOR_APPLE
+
+choice
+	prompt "Mainboard model"
+
+config BOARD_APPLE_MACBOOK21
+	bool "Macbook2,1"
+	help
+	  Consult wiki for details.
+
+endchoice
+
+source "src/mainboard/apple/macbook21/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "Apple"
+
+endif # VENDOR_APPLE
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
new file mode 100644
index 0000000000..a8b98303b5
--- /dev/null
+++ b/src/mainboard/apple/macbook21/Kconfig
@@ -0,0 +1,60 @@
+if BOARD_APPLE_MACBOOK21
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_MFCPGA478
+	select NORTHBRIDGE_INTEL_I945
+	select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
+	select SOUTHBRIDGE_INTEL_I82801GX
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select BOARD_ROMSIZE_KB_2048
+	select CHANNEL_XOR_RANDOMIZATION
+	select HAVE_ACPI_TABLES
+	select HAVE_ACPI_RESUME
+	select USE_OPTION_TABLE
+	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select MAINBOARD_DO_EDID
+	select EARLY_CBMEM_INIT
+	select INTEL_EDID
+
+config MAINBOARD_DIR
+	string
+	default apple/macbook21
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "MacBook2,1"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 2
+
+config MAINBOARD_SMBIOS_MANUFACTURER
+	string
+	default "Apple Inc."
+
+config SEABIOS_PS2_TIMEOUT
+	int
+	default 3000
+
+endif
diff --git a/src/mainboard/apple/macbook21/Makefile.inc b/src/mainboard/apple/macbook21/Makefile.inc
new file mode 100644
index 0000000000..1ba662e9f7
--- /dev/null
+++ b/src/mainboard/apple/macbook21/Makefile.inc
@@ -0,0 +1,19 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/apple/macbook21/acpi/ec.asl
diff --git a/src/mainboard/apple/macbook21/acpi/gpe.asl b/src/mainboard/apple/macbook21/acpi/gpe.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/apple/macbook21/acpi/gpe.asl
diff --git a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000000..6047def7ef
--- /dev/null
+++ b/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			Package() { 0x0001FFFF, 0, 0, 0x10 },
+			Package() { 0x0002FFFF, 0, 0, 0x10 },
+			Package() { 0x0007FFFF, 0, 0, 0x10 },
+			Package() { 0x001BFFFF, 0, 0, 0x16 },
+			Package() { 0x001CFFFF, 0, 0, 0x11 },
+			Package() { 0x001CFFFF, 1, 0, 0x10 },
+			Package() { 0x001CFFFF, 2, 0, 0x12 },
+			Package() { 0x001CFFFF, 3, 0, 0x13 },
+			Package() { 0x001DFFFF, 0, 0, 0x15 },
+			Package() { 0x001DFFFF, 1, 0, 0x13 },
+			Package() { 0x001DFFFF, 2, 0, 0x12 },
+			Package() { 0x001DFFFF, 3, 0, 0x10 },
+			Package() { 0x001EFFFF, 0, 0, 0x16 },
+			Package() { 0x001EFFFF, 1, 0, 0x14 },
+			Package() { 0x001FFFFF, 0, 0, 0x12 },
+			Package() { 0x001FFFFF, 1, 0, 0x13 },
+			Package() { 0x001FFFFF, 3, 0, 0x10 }
+		})
+	} Else {
+		Return (Package() {
+			Package() { 0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x0002FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x0007FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001BFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001CFFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001CFFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001CFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001CFFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001DFFFF, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001DFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001DFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001DFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001EFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001EFFFF, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			Package() { 0x001FFFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001FFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001FFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 }
+		})
+	}
+}
diff --git a/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000000..53549019bc
--- /dev/null
+++ b/src/mainboard/apple/macbook21/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 },
+		Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 },
+		Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 },
+		Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 },
+		Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 },
+		Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 },
+		Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 },
+		Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 },
+		Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 },
+		Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 },
+		Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 },
+		Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 },
+		Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 },
+		Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 },
+		Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 },
+		Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 },
+		Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 },
+		Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 },
+		Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 },
+		Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 },
+		Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }
+	})
+ } Else {
+	Return (Package() {
+		Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 },
+		Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 },
+		Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 },
+		Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 },
+		Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 },
+		Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 },
+		Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 },
+		Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 },
+		Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 },
+		Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 },
+		Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 },
+		Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 },
+		Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }
+	})
+}
diff --git a/src/mainboard/apple/macbook21/acpi/mainboard.asl b/src/mainboard/apple/macbook21/acpi/mainboard.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/apple/macbook21/acpi/mainboard.asl
diff --git a/src/mainboard/apple/macbook21/acpi/platform.asl b/src/mainboard/apple/macbook21/acpi/platform.asl
new file mode 100644
index 0000000000..1c6ac6e6c2
--- /dev/null
+++ b/src/mainboard/apple/macbook21/acpi/platform.asl
@@ -0,0 +1,192 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External(PDC0)
+External(PDC1)
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	// CPU specific part
+
+	// Notify PCI Express slots in case a card
+	// was inserted while a sleep state was active.
+
+	// Are we going to S3?
+	If (LEqual(Arg0, 3)) {
+		// ..
+	}
+
+	// Are we going to S4?
+	If (LEqual(Arg0, 4)) {
+		// ..
+	}
+
+	// TODO: Windows XP SP2 P-State restore
+
+	Return(Package(){0,0})
+}
+
+// Power notification
+
+External (\_PR_.CPU0, DeviceObj)
+External (\_PR_.CPU1, DeviceObj)
+
+Method (PNOT)
+{
+	If (MPEN) {
+		If(And(PDC0, 0x08)) {
+			Notify (\_PR_.CPU0, 0x80)	 // _PPC
+
+			If (And(PDC0, 0x10)) {
+				Sleep(100)
+				Notify(\_PR_.CPU0, 0x81) // _CST
+			}
+		}
+
+		If(And(PDC1, 0x08)) {
+			Notify (\_PR_.CPU1, 0x80)	 // _PPC
+			If (And(PDC1, 0x10)) {
+				Sleep(100)
+				Notify(\_PR_.CPU1, 0x81) // _CST
+			}
+		}
+
+	} Else { // UP
+		Notify (\_PR_.CPU0, 0x80)
+		Sleep(0x64)
+		Notify(\_PR_.CPU0, 0x81)
+	}
+}
+
+/* System Bus */
+
+Scope(\_SB)
+{
+	/* This method is placed on the top level, so we can make sure it's the
+	 * first executed _INI method.
+	 */
+	Method(_INI, 0)
+	{
+		/* The DTS data in NVS is probably not up to date.
+		 * Update temperature values and make sure AP thermal
+		 * interrupts can happen
+		 */
+
+		// TRAP(71) // TODO
+
+		/* Determine the Operating System and save the value in OSYS.
+		 * We have to do this in order to be able to work around
+		 * certain windows bugs.
+		 *
+		 *    OSYS value | Operating System
+		 *    -----------+------------------
+		 *       2000    | Windows 2000
+		 *       2001    | Windows XP(+SP1)
+		 *       2002    | Windows XP SP2
+		 *       2006    | Windows Vista
+		 *       ????    | Windows 7
+		 */
+
+		/* Let's assume we're running at least Windows 2000 */
+		Store (2000, OSYS)
+
+		If (CondRefOf(_OSI, Local0)) {
+			/* Linux answers _OSI with "True" for a couple of
+			 * Windows version queries. But unlike Windows it
+			 * needs a Video repost, so let's determine whether
+			 * we're running Linux.
+			 */
+
+			If (_OSI("Linux")) {
+				Store (1, LINX)
+			}
+
+			If (_OSI("Windows 2001")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP1")) {
+				Store (2001, OSYS)
+			}
+
+			If (_OSI("Windows 2001 SP2")) {
+				Store (2002, OSYS)
+			}
+
+			If (_OSI("Windows 2006")) {
+				Store (2006, OSYS)
+			}
+		}
+
+		/* And the OS workarounds start right after we know what we're
+		 * running: Windows XP SP1 needs to have C-State coordination
+		 * enabled in SMM.
+		 */
+		If (LAnd(LEqual(OSYS, 2001), MPEN)) {
+			// TRAP(61) // TODO
+		}
+
+		/* SMM power state and C4-on-C3 settings need to be updated */
+		// TRAP(43) // TODO
+	}
+}
+
diff --git a/src/mainboard/apple/macbook21/acpi/superio.asl b/src/mainboard/apple/macbook21/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/apple/macbook21/acpi/superio.asl
diff --git a/src/mainboard/apple/macbook21/acpi/video.asl b/src/mainboard/apple/macbook21/acpi/video.asl
new file mode 100644
index 0000000000..50a0947c2d
--- /dev/null
+++ b/src/mainboard/apple/macbook21/acpi/video.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+
+Device (DSPC)
+{
+	Name (_ADR, 0x00020001)
+	OperationRegion (DSPC, PCI_Config, 0x00, 0x100)
+	Field (DSPC, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0xf4),
+		       BRTC, 8
+	}
+
+	Method(BRTD, 0, NotSerialized)
+	{
+		Store(BRTC, Local0)
+		if (LGreater (Local0, 15))
+		{
+			Subtract(Local0, 16, Local0)
+			Store(Local0, BRTC)
+		}
+	}
+
+	Method(BRTU, 0, NotSerialized)
+	{
+		Store (BRTC, Local0)
+		if (LLess(Local0, 0xff))
+		{
+			Add (Local0, 16, Local0)
+			Store(Local0, BRTC)
+		}
+	}
+}
diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c
new file mode 100644
index 0000000000..f6ed4ae6dd
--- /dev/null
+++ b/src/mainboard/apple/macbook21/acpi_tables.c
@@ -0,0 +1,271 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/i82801gx/nvs.h"
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+
+	/* Enable both COM ports */
+	gnvs->cmap = 0x01;
+	gnvs->cmbp = 0x01;
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* LAPIC_NMI */
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+				current, 0,
+				MP_IRQ_POLARITY_HIGH |
+				MP_IRQ_TRIGGER_EDGE, 0x01);
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+				current, 1, MP_IRQ_POLARITY_HIGH |
+				MP_IRQ_TRIGGER_EDGE, 0x01);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
+
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+	void *gnvs;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	/* Fix up global NVS region for SMI handler. The GNVS region lives
+	 * in the (high) table area. The low memory map looks like this:
+	 *
+	 * 0x00000000 - 0x000003ff	Real Mode IVT
+	 * 0x00000020 - 0x0000019c	Low MP Table (XXX conflict?)
+	 * 0x00000400 - 0x000004ff	BDA (somewhat unused)
+	 * 0x00000500 - 0x0000052f	Moved GDT
+	 * 0x00000530 - 0x00000b64	coreboot table
+	 * 0x0007c000 - 0x0007dfff	OS boot sector (unused?)
+	 * 0x0007e000 - 0x0007ffff	free to use (so no good for acpi+smi)
+	 * 0x00080000 - 0x0009fbff	usable ram
+	 * 0x0009fc00 - 0x0009ffff	EBDA (unused?)
+	 * 0x000a0000 - 0x000bffff	VGA memory
+	 * 0x000c0000 - 0x000cffff	VGA option rom
+	 * 0x000d0000 - 0x000dffff	free for other option roms?
+	 * 0x000e0000 - 0x000fffff	SeaBIOS? (conflict with low tables:)
+	 * 0x000f0000 - 0x000f03ff	PIRQ table
+	 * 0x000f0400 - 0x000f66??	ACPI tables
+	 * 0x000f66?? - 0x000f????	DMI tables
+	 */
+
+	ALIGN_CURRENT;
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	/* Keep pointer around */
+	gnvs = (void *)current;
+
+	current += 0x100;
+	ALIGN_CURRENT;
+
+	/* And tell SMI about it */
+	smm_setup_structures(gnvs, NULL, NULL);
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+	printk(BIOS_INFO, "ACPI: done.\n");
+
+	/* Enable Dummy DCC ON# for DVI */
+	printk(BIOS_DEBUG, "Laptop handling...\n");
+	outb(inb(0x60f) & ~(1 << 5), 0x60f);
+
+	return current;
+}
diff --git a/src/mainboard/apple/macbook21/board_info.txt b/src/mainboard/apple/macbook21/board_info.txt
new file mode 100644
index 0000000000..b620278024
--- /dev/null
+++ b/src/mainboard/apple/macbook21/board_info.txt
@@ -0,0 +1,6 @@
+Board name: Macbook2,1
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
new file mode 100644
index 0000000000..0185e94f64
--- /dev/null
+++ b/src/mainboard/apple/macbook21/cmos.default
@@ -0,0 +1,21 @@
+boot_option=Fallback
+last_boot=Fallback
+baud_rate=115200
+debug_level=Spew
+hyper_threading=Enable
+nmi=Enable
+boot_devices=''
+boot_default=0x40
+cmos_defaults_loaded=Yes
+lpt=Enable
+volume=0x3
+tft_brightness=0xff
+first_battery=Primary
+bluetooth=Enable
+wlan=Enable
+wwan=Enable
+trackpoint=Enable
+fn_ctrl_swap=Disable
+sticky_fn=Disable
+power_management_beeps=Enable
+low_battery_beep=Enable
diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout
new file mode 100644
index 0000000000..469371e415
--- /dev/null
+++ b/src/mainboard/apple/macbook21/cmos.layout
@@ -0,0 +1,162 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       h       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+#409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+416        512       s       0        boot_devices
+928          8       h       0        boot_default
+936          1       e       8        cmos_defaults_loaded
+937          1       e       1        lpt
+#938         46       r       0        unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# ram initialization internal data
+1024         8       r       0        C0WL0REOST
+1032         8       r       0        C1WL0REOST
+1040         8       r       0        RCVENMT
+1048         4       r       0        C0DRT1
+1052         4       r       0        C1DRT1
+
+1064         8       h       0        volume
+1072         8       h       0        tft_brightness
+1080         1       e       9        first_battery
+1081         1       e       1        bluetooth
+1082         1       e       1        wwan
+1083         1       e       1        wlan
+1084         1       e       1        trackpoint
+1085         1       e       1        fn_ctrl_swap
+1086         1       e       1        sticky_fn
+1087         1       e       1        power_management_beeps
+1088         1       e       1        low_battery_beep
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+8     0     No
+8     1     Yes
+9     0	    Secondary
+9     1	    Primary
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
new file mode 100644
index 0000000000..6b1e7fff35
--- /dev/null
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -0,0 +1,108 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/i945
+
+	register "gpu_hotplug" = "0x00000220"
+	register "gpu_lvds_use_spread_spectrum_clock" = "1"
+	register "gpu_lvds_is_dual_channel" = "0"
+	register "gpu_backlight" = "0x1280128"
+
+	device cpu_cluster 0 on
+		chip cpu/intel/socket_mFCPGA478
+			device lapic 0 on end
+		end
+	end
+
+	device domain 0 on
+		device pci 00.0 on # Host bridge
+			subsystemid 0x8086 0x7270
+		end
+		device pci 02.0 on # VGA controller
+			subsystemid 0x8086 0x7270
+		end
+		device pci 02.1 on # display controller
+			subsystemid 0x17aa 0x201a
+		end
+		chip southbridge/intel/i82801gx
+			register "pirqa_routing" = "0x0b"
+			register "pirqb_routing" = "0x0b"
+			register "pirqc_routing" = "0x0b"
+			register "pirqd_routing" = "0x0b"
+			register "pirqe_routing" = "0x0b"
+			register "pirqf_routing" = "0x0b"
+			register "pirqg_routing" = "0x0b"
+			register "pirqh_routing" = "0x0b"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi13_routing" = "2"
+			register "gpi12_routing" = "1"
+			register "gpi8_routing" = "2"
+
+			register "sata_ahci" = "0x1"
+			register "sata_ports_implemented" = "0x04"
+
+			register "gpe0_en" = "0x11000006"
+			register "alt_gp_smi_en" = "0x1000"
+
+			register "ide_enable_primary" = "1"
+			register "ide_enable_secondary" = "1"
+
+			register "c4onc3_enable" = "1"
+			device pci 1b.0 on # Audio Controller
+				subsystemid 0x17aa 0x2010
+			end
+			device pci 1c.0 on end # Ethernet
+			device pci 1c.1 on end # Atheros WLAN
+			device pci 1d.0 on # USB UHCI
+				subsystemid 0x8086 0x7270
+			end
+			device pci 1d.1 on # USB UHCI
+				subsystemid 0x8086 0x7270
+			end
+			device pci 1d.2 on # USB UHCI
+				subsystemid 0x8086 0x7270
+			end
+			device pci 1d.3 on # USB UHCI
+				subsystemid 0x8086 0x7270
+			end
+			device pci 1d.7 on # USB2 EHCI
+				subsystemid 0x8086 0x7270
+			end
+			device pci 1f.0 on # PCI-LPC bridge
+				subsystemid 0x8086 0x7270
+			end
+			device pci 1f.1 on # IDE
+				subsystemid 0x8086 0x7270
+			end
+			device pci 1f.2 on # SATA
+				subsystemid 0x8086 0x7270
+			end
+			device pci 1f.3 on # SMBUS
+				subsystemid 0x8086 0x7270
+			end
+		end
+	end
+end
diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl
new file mode 100644
index 0000000000..e654d202dd
--- /dev/null
+++ b/src/mainboard/apple/macbook21/dsdt.asl
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#define THINKPAD_EC_GPE 28
+#define BRIGHTNESS_UP \DSPC.BRTU
+#define BRIGHTNESS_DOWN \DSPC.BRTD
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x03,		// DSDT revision: ACPI v3.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20090419	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+
+	// General Purpose Events
+	#include "acpi/gpe.asl"
+
+	// mainboard specific devices
+	#include "acpi/mainboard.asl"
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/i945/acpi/i945.asl>
+			#include <southbridge/intel/i82801gx/acpi/ich7.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/apple/macbook21/fadt.c b/src/mainboard/apple/macbook21/fadt.c
new file mode 100644
index 0000000000..06b0346d55
--- /dev/null
+++ b/src/mainboard/apple/macbook21/fadt.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 0x00;
+	fadt->preferred_pm_profile = PM_MOBILE;
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x20;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x28;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = APM_CNT_CST_CONTROL;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 0x23;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x32;
+	fadt->iapc_boot_arch = 0x00;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE;
+
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 0;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 0;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 0;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/apple/macbook21/irq_tables.c b/src/mainboard/apple/macbook21/irq_tables.c
new file mode 100644
index 0000000000..8991d7f69a
--- /dev/null
+++ b/src/mainboard/apple/macbook21/irq_tables.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * 15,		/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x1f << 3) | 0x0,	/* Interrupt router dev */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x122e,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xf5,			/* Checksum (has to be set to some value that
+				 * would give 0 after the sum of all bytes
+				 * for this structure (including checksum).
+                                 */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA       0:02.0 */
+		{0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio  0:1b.0 */
+		{0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.0 */
+		{0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.1 */
+		{0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.2 */
+		{0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe      0:1c.3 */
+		{0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.0 */
+		{0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.1 */
+		{0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.2 */
+		{0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB       0:1d.3 */
+		{0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI       0:1e.0 */
+		{0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC       0:1f.0 */
+		{0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE       0:1f.1 */
+		{0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA      0:1f.2 */
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c
new file mode 100644
index 0000000000..6bd3aec083
--- /dev/null
+++ b/src/mainboard/apple/macbook21/mainboard.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <delay.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <northbridge/intel/i945/i945.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/x86/include/arch/acpigen.h>
+#include <smbios.h>
+#include <x86emu/x86emu.h>
+#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(void)
+{
+	/* The right way to do this is to move this handler code into
+	 * the mainboard or northbridge code.
+	 * TODO: completely move to mainboards / chipsets.
+	 */
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+	       __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+	switch (X86_AX) {
+	case 0x5f35: /* Boot Display */
+		X86_AX = 0x005f; // Success
+		X86_CL = PANEL;
+		break;
+	case 0x5f40: /* Boot Panel Type */
+		X86_AX = 0x005f; // Success
+		X86_CL = 3;
+		printk(BIOS_DEBUG, "DISPLAY=%x\n", X86_CL);
+		break;
+	default:
+		/* Interrupt was not handled */
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+		return 0;
+	}
+
+	/* Interrupt handled */
+	return 1;
+}
+#endif
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+	return 0;
+}
+
+static void mainboard_init(device_t dev)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	/* Install custom int15 handler for VGA OPROM */
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c
new file mode 100644
index 0000000000..cc97e52377
--- /dev/null
+++ b/src/mainboard/apple/macbook21/mptable.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <string.h>
+#include <stdint.h>
+
+static void *smp_write_config_table(void *v)
+{
+        struct mp_config_table *mc;
+	int isa_bus;
+
+        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LOCAL_APIC_ADDR);
+
+        smp_write_processors(mc);
+
+	mptable_write_buses(mc, NULL, &isa_bus);
+
+	/* I/O APICs:	APIC ID	Version	State		Address */
+	smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+
+	/* Legacy Interrupts */
+	mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
+
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00);
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2),       0x02, 0x10);  /* PCIe root 0.02.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2),       0x02, 0x10);  /* VGA       0.02.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2),       0x02, 0x16);  /* HD Audio  0:1b.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2),       0x02, 0x11);  /* PCIe      0:1c.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x10); /* PCIe      0:1c.1 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x12); /* PCIe      0:1c.2 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x13); /* PCIe      0:1c.3 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2)       , 0x02, 0x15); /* USB       0:1d.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x13); /* USB       0:1d.1 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB       0:1d.2 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x10); /* USB       0:1d.3 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2)       , 0x02, 0x12); /* LPC       0:1f.0 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x13); /* IDE       0:1f.1 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x03, 0x02, 0x10); /* SATA      0:1f.3 */
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x03, (0x03 << 2)       , 0x02, 0x13); /* Firewire   3:03.0 */
+
+	mptable_lintsrc(mc, isa_bus);
+	return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
new file mode 100644
index 0000000000..e7ff902a2d
--- /dev/null
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -0,0 +1,414 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <cbmem.h>
+#include <timestamp.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+
+void setup_ich7_gpios(void)
+{
+	printk(BIOS_DEBUG, " GPIOS...");
+
+	/* X60 GPIO:
+	 * 1: HDD_PRESENCE#
+	 * 6: Unknown (Pulled high by R215 to VCC3B)
+	 * 7: BDC_PRESENCE#
+	 * 8: H8_WAKE#
+	 * 9: RTC_BAT_IN#
+	 * 10: Unknown (Pulled high by R700 to VCC3M)
+	 * 12: H8SCI#
+	 * 13: SLICE_ON_3M#
+	 * 14: Unknown (Pulled high by R321 to VCC3)
+	 * 15: Unknown (Pulled high by R258 to VCC3)
+	 * 19: Unknown (Pulled low  by R594)
+	 * 21: Unknown (Pulled high by R145 to VCC3)
+	 * 22: FWH_WP#
+	 * 25: MDC_KILL#
+	 * 33: HDD_PRESENCE_2#
+	 * 35: CLKREQ_SATA#
+	 * 36: PLANARID0
+	 * 37: PLANARID1
+	 * 38: PLANARID2
+	 * 39: PLANARID3
+	 * 48: FWH_TBL#
+	 */
+
+	outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
+	outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
+	outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
+	/* Output Control Registers */
+	outl(0x00000000, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
+	/* Input Control Registers */
+	outl(0x00002082, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
+	outl(0x000100c0, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
+	outl(0x00000030, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
+	outl(0x000100c0, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL2 */
+}
+
+static void ich7_enable_lpc(void)
+{
+	// Enable Serial IRQ
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+
+	// I/O Decode Ranges
+	// X60:       0x0210 == 00000010 00010000
+	// Macbook21: 0x0010 == 00000000 00010000
+	// Bit 9:8    LPT Decode Range. This field determines which range to
+	//            decode for the LPT Port.
+	//            00 = 378h ­ 37Fh and 778h ­ 77Fh
+	//            10 = 3BCh ­ 3BEh and 7BCh ­ 7BEh
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+
+	// LPC_EN--LPC I/F Enables Register
+	// X60:       0x1f0d == 00011111 00001101
+	// Macbook21: 0x3807 == 00111000 00000111
+	// Bit 13     CNF2_LPC_EN -- R/W. Microcontroller Enable # 2.
+	//            0 = Disable.
+	//            1 = Enables the decoding of the I/O locations 4Eh and 4Fh
+	//            to the LPC interface. This range is used for a
+	//            microcontroller.
+	// Bit 12     CNF1_LPC_EN -- R/W. Super I/O Enable.
+	//            0 = Disable.
+	//            1 = Enables the decoding of the I/O locations 2Eh and 2Fh
+	//            to the LPC interface. This range is used for
+	//            Super I/O devices.
+	// Bit 11     MC_LPC_EN -- R/W. Microcontroller Enable # 1.
+	//            0 = Disable.
+	//            1 = Enables the decoding of the I/O locations 62h and 66h
+	//            to the LPC interface. This range is used for a
+	//            microcontroller.
+	// Bit 10     KBC_LPC_EN -- R/W. Keyboard Enable.
+	//            0 = Disable.
+	//            1 = Enables the decoding of the I/O locations 60h and 64h
+	//            to the LPC interface. This range is used for a
+	//            microcontroller.
+	// Bit 9      GAMEH_LPC_EN -- R/W. High Gameport Enable
+	//            0 = Disable.
+	//            1 = Enables the decoding of the I/O locations 208h to 20Fh
+	//            to the LPC interface. This range is used for a gameport.
+	// Bit 8      GAMEL_LPC_EN -- R/W. Low Gameport Enable
+	//            0 = Disable.
+	//            1 = Enables the decoding of the I/O locations 200h to 207h
+	//            to the LPC interface. This range is used for a gameport.
+	// Bit 3      FDD_LPC_EN -- R/W. Floppy Drive Enable
+	//            0 = Disable.
+	//            1 = Enables the decoding of the FDD range to the LPC
+	//            interface. This range is selected in the LPC_FDD/LPT
+	//            Decode Range Register (D31:F0:80h, bit 12).
+	// Bit 2      LPT_LPC_EN -- R/W. Parallel Port Enable
+	//            0 = Disable.
+	//            1 = Enables the decoding of the LPT range to the LPC
+	//            interface. This range is selected in the LPC_FDD/LPT
+	//            Decode Range Register (D31:F0:80h, bit 9:8).
+	// Bit 1      COMB_LPC_EN -- R/W. Com Port B Enable
+	//            0 = Disable.
+	//            1 = Enables the decoding of the COMB range to the LPC
+	//            interface. This range is selected in the LPC_COM Decode
+	//            Range Register (D31:F0:80h, bits 6:4).
+	// Bit 0      COMA_LPC_EN -- R/W. Com Port A Enable
+	//            0 = Disable.
+	//            1 = Enables the decoding of the COMA range to the LPC
+	//            interface. This range is selected in the LPC_COM Decode
+	//            Range Register (D31:F0:80h, bits 3:2).
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807);
+
+	/* GEN1_DEC, LPC Interface Generic Decode Range 1 */
+	// X60:       0x1601 0x007c == 00000000 01111100 00010110 00000001
+	// Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001
+	// Bit 31:24  Reserved.
+	// Bit 23:18  Generic I/O Decode Range Address[7:2] Mask: A `1' in any
+	//            bit position indicates that any value in the corresponding
+	//            address bit in a received cycle will be treated as a
+	//            match. The corresponding bit in the Address field, below,
+	//            is ignored. The mask is only provided for the lower 6 bits
+	//            of the DWord address, allowing for decoding blocks up to
+	//            256 bytes in size.
+	// Bit 17:16  Reserved.
+	// Bit 15:2   Generic I/O Decode Range 1 Base Address (GEN1_BASE). This
+	//            address is aligned on a 128-byte boundary, and must have
+	//            address lines 31:16 as 0. NOTE: The Intel ICH7 does not
+	//            provide decode down to the word or byte level.
+	// Bit 1      Reserved.
+	// Bit 0      Generic Decode Range 1 Enable (GEN1_EN) -- R/W.
+	//            0 = Disable.
+	//            1 = Enable the GEN1 I/O range to be forwarded to the LPC
+	//            I/F
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c);
+
+	/* GEN2_DEC, LPC Interface Generic Decode Range 2 */
+	// X60:       0x15e1 0x000c == 00000000 00001100 00010101 11100001
+	// Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c);
+
+	/* GEN3_DEC, LPC Interface Generic Decode Range 3 */
+	// X60:       0x1681 0x001c == 00000000 00011100 00010110 10000001
+	// Macbook21: 0x0000 0x0000
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros?
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000);
+
+	/* GEN4_DEC, LPC Interface Generic Decode Range 4 */
+	// X60:       0x0000 0x0000
+	// Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c);
+}
+
+static void rcba_config(void)
+{
+	/* V0CTL Virtual Channel 0 Resource Control */
+	RCBA32(0x0014) = 0x80000001;
+	/* V1CAP Virtual Channel 1 Resource Capability */
+	RCBA32(0x001c) = 0x03128010;
+
+	/* Device 1f interrupt pin register */
+	RCBA32(0x3100) = 0x00042210;
+	RCBA32(0x3108) = 0x10004321;
+
+	/* PCIe Interrupts */
+	RCBA32(0x310c) = 0x00214321;
+	/* HD Audio Interrupt */
+	RCBA32(0x3110) = 0x00000001;
+
+	/* dev irq route register */
+	RCBA16(0x3140) = 0x0232;
+	RCBA16(0x3142) = 0x3246;
+	RCBA16(0x3144) = 0x0235;
+	RCBA16(0x3146) = 0x3201;
+	RCBA16(0x3148) = 0x3216;
+
+	/* Enable IOAPIC */
+	RCBA8(0x31ff) = 0x03;
+
+	/* Enable upper 128bytes of CMOS */
+	RCBA32(0x3400) = (1 << 2);
+
+	/* Disable unused devices */
+	RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
+	RCBA32(0x3418) |= (1 << 0);	// Required.
+
+	/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
+	//	RCBA32(0x1e84) = 0x00020001;
+	//	RCBA32(0x1e80) = 0x0000fe01;
+
+	/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+	RCBA32(0x1e9c) = 0x000200f0;
+	RCBA32(0x1e98) = 0x000c0801;
+}
+
+static void early_ich7_init(void)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+
+	// program secondary mlt XXX byte?
+	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+	// reset rtc power status
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+	// usb transient disconnect
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+	reg8 |= (3 << 0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+	reg32 |= (1 << 29) | (1 << 17);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+	reg32 |= (1 << 31) | (1 << 27);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+	RCBA32(0x0088) = 0x0011d000;
+	RCBA16(0x01fc) = 0x060f;
+	RCBA32(0x01f4) = 0x86000040;
+	RCBA32(0x0214) = 0x10030549;
+	RCBA32(0x0218) = 0x00020504;
+	RCBA8(0x0220) = 0xc5;
+	reg32 = RCBA32(0x3410);
+	reg32 |= (1 << 6);
+	RCBA32(0x3410) = reg32;
+	reg32 = RCBA32(0x3430);
+	reg32 &= ~(3 << 0);
+	reg32 |= (1 << 0);
+	RCBA32(0x3430) = reg32;
+	RCBA32(0x3418) |= (1 << 0);
+	RCBA16(0x0200) = 0x2008;
+	RCBA8(0x2027) = 0x0d;
+	RCBA16(0x3e08) |= (1 << 7);
+	RCBA16(0x3e48) |= (1 << 7);
+	RCBA32(0x3e0e) |= (1 << 7);
+	RCBA32(0x3e4e) |= (1 << 7);
+
+	// next step only on ich7m b0 and later:
+	reg32 = RCBA32(0x2034);
+	reg32 &= ~(0x0f << 16);
+	reg32 |= (5 << 16);
+	RCBA32(0x2034) = reg32;
+}
+
+void main(unsigned long bist)
+{
+	u32 reg32;
+	int boot_mode = 0;
+	int cbmem_was_initted;
+	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 };
+
+
+	timestamp_init(get_initial_timestamp());
+	timestamp_add_now(TS_START_ROMSTAGE);
+
+	if (bist == 0)
+		enable_lapic();
+
+	/* Force PCIRST# */
+	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+	udelay(200 * 1000);
+	pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
+
+	ich7_enable_lpc();
+
+	/* Set up the console */
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG,
+		       "Soft reset detected, rebooting properly.\n");
+		outb(0x6, 0xcf9);
+		while (1)
+			asm("hlt");
+	}
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	i945_early_initialization();
+
+	/* Read PM1_CNT */
+	reg32 = inl(DEFAULT_PMBASE + 0x04);
+	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
+	if (((reg32 >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+	}
+
+	/* Enable SPD ROMs and DDR-II DRAM */
+	enable_smbus();
+
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	dump_spd_registers();
+#endif
+
+	timestamp_add_now(TS_BEFORE_INITRAM);
+	sdram_initialize(boot_mode, spd_addrmap);
+	timestamp_add_now(TS_AFTER_INITRAM);
+
+	/* Perform some initialization that must run before stage2 */
+	early_ich7_init();
+
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
+	 */
+	rcba_config();
+
+	/* Chipset Errata! */
+	fixup_i945_errata();
+
+	/* Initialize the internal PCIe links before we go into stage2 */
+	i945_late_initialization();
+
+#if !CONFIG_HAVE_ACPI_RESUME
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+#if CONFIG_DEBUG_RAM_SETUP
+	sdram_dump_mchbar_registers();
+
+	{
+		/* This will not work if TSEG is in place! */
+		u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c);
+
+		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
+		ram_check(0x00000000, 0x000a0000);
+		ram_check(0x00100000, tom);
+	}
+#endif
+#endif
+#endif
+
+	MCHBAR16(SSKPD) = 0xCAFE;
+
+	cbmem_was_initted = !cbmem_recovery(boot_mode==2);
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+	if ((boot_mode == 2) && cbmem_was_initted) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+
+		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+		 * through stage 2. We could keep stuff like stack and heap in high tables
+		 * memory completely, but that's a wonderful clean up task for another
+		 * day.
+		 */
+		if (resume_backup_memory)
+			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
+			       HIGH_MEMORY_SAVE);
+
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
+				   SKPAD_ACPI_S3_MAGIC);
+	}
+#endif
+
+	timestamp_add_now(TS_END_ROMSTAGE);
+
+}
diff --git a/src/mainboard/apple/macbook21/smi.h b/src/mainboard/apple/macbook21/smi.h
new file mode 100644
index 0000000000..92186bff09
--- /dev/null
+++ b/src/mainboard/apple/macbook21/smi.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef MAINBOARD_APPLE_MACBOOK21_SMI_H
+#define MAINBOARD_APPLE_MACBOOK21_SMI_H
+
+#endif
diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c
new file mode 100644
index 0000000000..0b3d615eb7
--- /dev/null
+++ b/src/mainboard/apple/macbook21/smihandler.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+#include <pc80/mc146818rtc.h>
+#include <delay.h>
+#include "smi.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+	printk(BIOS_DEBUG, "initializing SMI\n");
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+	static int smm_initialized;
+
+	if (!smm_initialized) {
+		mainboard_smm_init();
+		smm_initialized = 1;
+	}
+
+	switch (smif) {
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 1
+	 * On failure, the IO Trap Handler returns a value != 1 */
+	return 1;
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+	u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+	u8 tmp;
+
+	printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
+
+	if (!pmbase)
+		return 0;
+
+	switch(data) {
+		case APM_CNT_ACPI_ENABLE:
+			/* route H8SCI to SCI */
+			outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+			tmp &= ~0x03;
+			tmp |= 0x02;
+			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+			break;
+		case APM_CNT_ACPI_DISABLE:
+			/* route H8SCI# to SMI */
+			outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
+			tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+			tmp &= ~0x03;
+			tmp |= 0x01;
+			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+			break;
+		default:
+			break;
+	}
+	return 0;
+}