diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-10-30 16:48:19 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-01 11:50:03 +0000 |
| commit | 2715cdb3f32fcebdd1de6870a665a2b613c07e60 (patch) | |
| tree | 5addc7091dfc055927c7edbbb44f36a45114e77c /src/mainboard/apple | |
| parent | 1e8f305957c98cb224574e1fa81938c9a692bd48 (diff) | |
| download | coreboot-2715cdb3f32fcebdd1de6870a665a2b613c07e60.tar.xz | |
soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi
This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/apple')
| -rw-r--r-- | src/mainboard/apple/macbook21/dsdt.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/apple/macbookair4_2/dsdt.asl | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index 830c0c8741..40af217c47 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -46,5 +46,5 @@ DefinitionBlock( } /* Chipset specific sleep states */ - #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index 65ce63ea6e..641b951bb5 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> Scope (\_SB) { Device (PCI0) |