Artec Group dbe61 mainboard support.

Now uses CAR.
New code for SPD-less memory implementation.
Updated IRQ routing.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 48 insertions, 80 deletions

diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb
index 97975e7c36..40f157f6e9 100644
--- a/src/mainboard/artecgroup/dbe61/Config.lb
+++ b/src/mainboard/artecgroup/dbe61/Config.lb
@@ -47,27 +47,17 @@ driver mainboard.o
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
 
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+if USE_DCACHE_RAM
+	#compile cache_as_ram.c to auto.inc
+	makerule ./cache_as_ram_auto.inc
+			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+			action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+			action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+	end
 end
 
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
 
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
@@ -104,7 +94,7 @@ ldscript /arch/i386/lib/id.lds
 ###
 if USE_FALLBACK_IMAGE
 	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
+#	mainboardinit ./failover.inc
 end
 
 ###
@@ -115,7 +105,11 @@ end
 ## Setup RAM
 ##
 mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit ./auto.inc
+
+if USE_DCACHE_RAM
+	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
+	mainboardinit ./cache_as_ram_auto.inc
+end
 
 ##
 ## Include the secondary Configuration files 
@@ -124,70 +118,44 @@ dir /pc80
 config chip.h
 
 chip northbridge/amd/lx
-	register "irqmap" = "0xcba5"
+	device pci_domain 0 on
+		device pci 1.0 on end	# Northbridge
+		device pci 1.1 on end	# Graphics
+		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+			register "lpc_serirq_enable" = "0x00001002"
+			register "lpc_serirq_polarity" = "0x0000EFFD"
+			register "lpc_serirq_mode" = "1"
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "0"	#0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "0"
+			register "com1_address" = "0x2F8"
+			register "com1_irq" = "3"
+			register "com2_enable" = "1"
+			register "com2_address" = "0x3F8"
+			register "com2_irq" = "4"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+			device pci b.0 on end	# Slot 3
+			device pci c.0 on end	# Slot 4
+			device pci d.0 on end	# Slot 1
+			device pci e.0 on end	# Slot 2
+			device pci f.0 on end	# ISA Bridge
+			device pci f.2 on end	# IDE Controller
+			device pci f.3 on end	# Audio
+			device pci f.4 on end	# OHCI
+			device pci f.5 on end	# EHCI
+		end
+	end
+	# APIC cluster is late CPU init.
 	device apic_cluster 0 on
 		chip cpu/amd/model_lx
 			device apic 0 on end
 		end
 	end
-  	device pci_domain 0 on 
-
- 		device pci 1.0 on end	# Host Bridge
- 
-# 		chip drivers/pci/realmode
-# 			device pci 1.1 on end  					# VGA
-# 			register "rom_address" = "0xfffc0000"	# at the beginning of 256k
-# 		end
- 		
- 		device pci 1.2 off end	# AES
-     		chip southbridge/amd/cs5536_lx
- 			register "enable_ide_nand_flash" = "0"
- 
- 			register "isa_irq" = "0"
- 			#register "flash_irq" = "14"
- 
- 			## IDE IRQ
- 			register "enable_ide_irq" = "0"
- 
- 			register "audio_irq" = "5"
- 			register "usb_irq" = "7"
- 			
- 			register "uart0_irq" = "0"
- 			register "uart1_irq" = "4"
- 
- 			## PCI INTA ... INTD and their GPIO pins
- 			##   int==0: disable 
- 			register "pci_int[0]" = "0"
- 			register "pci_int[1]" = "10"
- 			register "pci_int[2]" = "0"
- 			register "pci_int[3]" = "0"
- 			register "pci_int_pin[0]" = "0"
- 			register "pci_int_pin[1]" = "7"
- 			register "pci_int_pin[2]" = "0"
- 			register "pci_int_pin[3]" = "0"									
- 
- 
- 			# Keyboard Emulation Logic IRQs
- 			# Enable keyboard IRQ2
- 			register "enable_kel_keyb_irq" = "0"
- 			# Enable mouse IRQ12
- 			register "enable_kel_mouse_irq" = "0"
- 			# Configure KEL Emulation IRQ, 0 to disable
- 			register "kel_emul_irq" = "0"
- 
-       		device pci f.0 on end	# ISA Bridge
-			device pci f.1 on end	# Flash controller
- 			device pci f.2 off end	# IDE controller
-       		device pci f.3 on end 	# Audio
-        		device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
- 			device pci f.6 off end	# UDC controller
- 			device pci f.7 off end	# OTG controller
- 		end
-# 		chip drivers/pci/rtl8139
-## 			device pci d.0 on end	# Realtek LAN
-# 			register "nic_irq" = "10"
-#        		end
-   	end
+
 end