diff options
author | Ron Minnich <Ron Minnich> | 2006-07-28 16:06:16 +0000 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-07-28 16:06:16 +0000 |
commit | 5e9dc231209c1a293b5a92a9ea78eb07ce0a3086 (patch) | |
tree | 00c90e50087fba91bf5fb2cab050b3191b1daf46 /src/mainboard/artecgroup/dbe61/failover.c | |
parent | e534daa05ae7057ad615e15fa3021b19f4850fd0 (diff) | |
download | coreboot-5e9dc231209c1a293b5a92a9ea78eb07ce0a3086.tar.xz |
This patch adds support for the AMD LX cpu.
There is one global change to pci_ids.h. The rest are changes for LX. I
ran abuild and it is ok. Not all artec design changes are included as
some of them would adversely affect other mainboards. Indrek will need
to test.
Signed-off-by: Ron Minnich
Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec
design.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/artecgroup/dbe61/failover.c')
-rw-r--r-- | src/mainboard/artecgroup/dbe61/failover.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/artecgroup/dbe61/failover.c b/src/mainboard/artecgroup/dbe61/failover.c new file mode 100644 index 0000000000..bdcb9eaed2 --- /dev/null +++ b/src/mainboard/artecgroup/dbe61/failover.c @@ -0,0 +1,32 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + /* This is the primary cpu how should I boot? */ + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} |