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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-07 17:38:01 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-09 21:39:18 +0200 |
| commit | 8d94fbd9997ee5ebc9d2a373b56672c8fa865255 (patch) | |
| tree | f131cc0c6ea75176a6e01f8178178785814220f8 /src/mainboard/artecgroup/dbe61/romstage.c | |
| parent | aacd548c26f251583f1035d4ecc544198721f937 (diff) | |
| download | coreboot-8d94fbd9997ee5ebc9d2a373b56672c8fa865255.tar.xz | |
mainboard/artecgroup: Use C89 comments style & remove commented code
Change-Id: Ia1e7f558bbc44001358339a522e59a2ef7c420fb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16923
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/artecgroup/dbe61/romstage.c')
| -rw-r--r-- | src/mainboard/artecgroup/dbe61/romstage.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index b0bfc5b128..7cf902ef8d 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -87,16 +87,4 @@ void main(unsigned long bist) cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); sdram_initialize(1, memctrl); - - /* Dump memory configuration. */ -#if 0 - msr = rdmsr(MC_CF07_DATA); - printk(BIOS_DEBUG, "MC_CF07_DATA: %08x value is: %08x:%08x\n", MC_CF07_DATA, msr.hi, msr.lo); - - msr = rdmsr(MC_CF1017_DATA); - printk(BIOS_DEBUG, "MC_CF1017_DATA: %08x value is: %08x:%08x\n", MC_CF07_DATA, msr.hi, msr.lo); - - msr = rdmsr(MC_CF8F_DATA); - printk(BIOS_DEBUG, "MC_CF8F_DATA: %08x value is: %08x:%08x\n", MC_CF07_DATA, msr.hi, msr.lo); -#endif } |