diff options
| author | Shelley Chen <shchen@chromium.org> | 2018-01-26 12:50:54 -0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2018-01-29 18:26:45 +0000 |
| commit | e87d3cdf59e6457e04158715789066d47d6e30e0 (patch) | |
| tree | f04b91d976ab4ca7f73cc0f9dff21fa8bbb318ba /src/mainboard/artecgroup | |
| parent | 339e771055ff8f7d1f9652cb4d68be6b15e97016 (diff) | |
| download | coreboot-e87d3cdf59e6457e04158715789066d47d6e30e0.tar.xz | |
google/fizz: Adjust PL2 and PsysPl2 values for power loss
Set PsysPl2 values to 90% of max adapter power for all types of
adapters (typeC and barrel jack) to account for a 10% power loss from
the adapter to the soc.
BUG=b:71594855
BRANCH=None
TEST=reboot device and make sure Pl2 and PsysPl2 MSRs are properly set
with iotools rdmsr command on both U42 and U22 skus with both
typeC and barrel jack power adapters.
Change-Id: I8425c6d4d669449eccb9324ff58ff6d1662c5c43
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/artecgroup')
0 files changed, 0 insertions, 0 deletions