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authorIndrek Kruusa <indrek.kruusa@artecdesign.ee>2006-08-03 16:48:18 +0000
committerStefan Reinauer <stepan@openbios.org>2006-08-03 16:48:18 +0000
commit8e3464109e47945b1a4d7e3dd0c6e291593de70a (patch)
tree03493e297dc332c8c7613303eb874e12830e0a5a /src/mainboard/artecgroup
parent8ad7c06535694959952b7d64a9649cb9534abd2a (diff)
downloadcoreboot-8e3464109e47945b1a4d7e3dd0c6e291593de70a.tar.xz
Changelog:
* src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/artecgroup')
-rw-r--r--src/mainboard/artecgroup/dbe61/Config.lb18
-rw-r--r--src/mainboard/artecgroup/dbe61/Options.lb9
-rw-r--r--src/mainboard/artecgroup/dbe61/irq_tables.c45
-rw-r--r--src/mainboard/artecgroup/dbe61/mainboard.c44
4 files changed, 73 insertions, 43 deletions
diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb
index a343b31edb..085685279b 100644
--- a/src/mainboard/artecgroup/dbe61/Config.lb
+++ b/src/mainboard/artecgroup/dbe61/Config.lb
@@ -124,8 +124,8 @@ dir /pc80
config chip.h
chip northbridge/amd/lx
- register "irqmap" = "0xcab9"
- register "setupflash" = "0"
+ register "irqmap" = "0xcba5"
+ register "setupflash" = "1"
device apic_cluster 0 on
chip cpu/amd/model_lx
device apic 0 on end
@@ -138,20 +138,18 @@ chip northbridge/amd/lx
register "enable_gpio0_inta" = "1"
register "enable_ide_nand_flash" = "1"
register "enable_uarta" = "1"
- register "audio_irq" = "5"
- register "usbf4_irq" = "10"
- register "usbf5_irq" = "10"
- register "usbf6_irq" = "0"
- register "usbf7_irq" = "0"
+ register "audio_irq" = "11"
+ register "usbf4_irq" = "5"
+ register "usbf5_irq" = "5"
+ register "usbf6_irq" = "5"
+ register "usbf7_irq" = "5"
device pci d.0 on end # Realtek 8139 LAN
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
- register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
- register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
- register "unwanted_vpci[2]" = "0" # End of list has a zero
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
end
end
end
diff --git a/src/mainboard/artecgroup/dbe61/Options.lb b/src/mainboard/artecgroup/dbe61/Options.lb
index fccf121786..1112fcee2c 100644
--- a/src/mainboard/artecgroup/dbe61/Options.lb
+++ b/src/mainboard/artecgroup/dbe61/Options.lb
@@ -71,8 +71,9 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=2
+default HAVE_PIRQ_TABLE=0
+default IRQ_SLOT_COUNT=6
+
#object irq_tables.o
##
@@ -112,8 +113,8 @@ default CONFIG_ROM_STREAM = 1
## The default compiler
##
default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc-3.4 -m32"
-default HOSTCC="gcc-3.4"
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
##
## The Serial Console
diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c
index 636f129119..4322e20e9b 100644
--- a/src/mainboard/artecgroup/dbe61/irq_tables.c
+++ b/src/mainboard/artecgroup/dbe61/irq_tables.c
@@ -7,24 +7,53 @@
#include <arch/pirq_routing.h>
-const struct irq_routing_table intel_irq_routing_table = {
+#define ID_SLOT_PCI_NET 1 // ThinCan ethernet
+#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1
+#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2
+#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3
+#define ID_EMBED_PCI 0xff // onboard PCI device
+
+// CS5535 PCI INT[A-D] Interrupt Routing lines.
+#define NO_CONNECT 0 // not used
+#define CS_PCI_INTA 1 // PCI INTA
+#define CS_PCI_INTB 2 // PCI INTB
+#define CS_PCI_INTC 3 // PCI INTC
+#define CS_PCI_INTD 4 // PCI INTD
+
+// IRQ bitmap reference line FEDCBA9876543210
+// 0000110000100000b
+#define PCI_IRQ 0xc20 // PCI allowed IRQs here
+
+const struct irq_routing_table intel_irq_routing_table =
+{
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
- 32+16*2, /* there can be total 2 devices on the bus */
+ 32+16*6, /* there can be total 2 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
- 0x800, /* IRQs devoted exclusively to PCI usage */
- 0x1078, /* Vendor */
- 0x2, /* Device */
- 0, /* Crap (miniport) */
+ 0x0800, /* IRQs devoted exclusively to PCI usage */
+ 0x1022, /* Vendor */
+ 0x208f, /* Device */
+ 0x00000000, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
- {0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
+ // Geode GX3 Host Bridge and VGA Graphics
+ {0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
+ // Realtek RTL8100/8139 Network Controller
+ {0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0},
+ // Reserved for future extensions
+ {0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0},
+ // Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
+ {0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
+ // Reserved for future extensions
+ {0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0},
+ // Reserved for future extensions
+ {0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0}
}
};
+
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
diff --git a/src/mainboard/artecgroup/dbe61/mainboard.c b/src/mainboard/artecgroup/dbe61/mainboard.c
index 2079443359..c95ca159f4 100644
--- a/src/mainboard/artecgroup/dbe61/mainboard.c
+++ b/src/mainboard/artecgroup/dbe61/mainboard.c
@@ -7,31 +7,33 @@
#include "chip.h"
-
-static void init(struct device *dev) {
-/*
+static void init(struct device *dev)
+{
unsigned bus = 0;
- unsigned devfn = PCI_DEVFN(0xf, 4);
- device_t usb = NULL;
- unsigned char usbirq = 0xa;
-*/
+ unsigned devNic = PCI_DEVFN(0xd, 0);
+ unsigned devUsb = PCI_DEVFN(0xf, 4);
+ device_t usb = NULL, nic = NULL;
+ unsigned char irqUsb = 0xa, irqNic = 0xb;
printk_debug("ARTECGROUP DBE61 ENTER %s\n", __FUNCTION__);
-#if 0
- /* I can't think of any reason NOT to just set this. If it turns out we want this to be
- * conditional we can make it a config variable later.
- */
-
- printk_debug("%s (%x,%x)SET USB PCI interrupt line to %d\n",
- __FUNCTION__, bus, devfn, usbirq);
- usb = dev_find_slot(bus, devfn);
- if (! usb){
- printk_err("Could not find USB\n");
- } else {
- pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq);
- }
-#endif
+ // FIXME: do we need to initialize USB OHCI this way?
+ printk_debug("%s (%x,%x) set USB PCI interrupt line to %d\n",
+ __FUNCTION__, bus, devUsb, irqUsb);
+
+ // initialize the USB controller
+ usb = dev_find_slot(bus, devUsb);
+ if (!usb) printk_err("Could not find USB\n");
+ else pci_write_config8(usb, PCI_INTERRUPT_LINE, irqUsb);
+
+ printk_debug("%s (%x,%x) set NIC PCI interrupt line to %d\n",
+ __FUNCTION__, bus, devNic, irqNic);
+
+ // initialize the Realtek NIC
+ nic = dev_find_slot(bus, devNic);
+ if (!nic) printk_err("Could not find USB\n");
+ else pci_write_config8(nic, PCI_INTERRUPT_LINE, irqNic);
+
printk_debug("ARTECGROUP DBE61 EXIT %s\n", __FUNCTION__);
}