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| author | Edwin Beasant <edwin_beasant@virtensys.com> | 2010-06-10 15:24:57 +0000 |
|---|---|---|
| committer | Edwin Beasant <edwin_beasant@virtensys.com> | 2010-06-10 15:24:57 +0000 |
| commit | f333ba09580c00a6f27e3ee0796431f5df936ecf (patch) | |
| tree | d9d961b45e248d59bf8e3e582b1619887d1921b9 /src/mainboard/artecgroup | |
| parent | 1965a237124cc8e988cf760eb7e9a61efb2adabb (diff) | |
| download | coreboot-f333ba09580c00a6f27e3ee0796431f5df936ecf.tar.xz | |
This commit updates the Geode LX GLCP delay control setup from the v2 way to the v3 way.
This resolves problems with terminated DRAM modules.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Roland G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/artecgroup')
| -rw-r--r-- | src/mainboard/artecgroup/dbe61/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 48be6820c7..4e9c9788f7 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -109,7 +109,7 @@ void main(unsigned long bist) pll_reset(ManualConf); - cpuRegInit(); + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); sdram_initialize(1, memctrl); |